CY7C924ADX-AXC Cypress Semiconductor Corp, CY7C924ADX-AXC Datasheet - Page 38

• Manufacturer Part Number: CY7C924ADX-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transceiverr

Specifications of CY7C924ADX-AXC

• Package / Case: 100-LQFP
• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 622 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage (typ): 5V
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• No. Of Receivers: 2
• Frequency Max: 50MHz
• Rohs Compliant: Yes
• Termination Type: SMD
• Filter Terminals: SMD
• Driver Case Style: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-2918; CY7C924ADX-AXC

significant impact on the actual data being transported across
the link. It may also be used to transparently propagate FIFO flow
control information across the link by directly connecting the
RXHALF* flag of the local receiver to the TXINT of the local trans-
mitter. The RXINT at the remote end of the link can then be
connected to the TXHALT* input to halt data transfers at the
remote end of the link until the local Receive FIFO has sufficient
room to continue.
Asynchronous Byte-Packed
Asynchronous byte-packed mode contains the same features as
asynchronous encoded, but with support for 10-bit source data.
This data is byte-packed through the 8B/10B encoder to deliver
the data across the interface. This mode is enabled when
FIFOBYP* and ENCBYP* are HIGH and BYTE8/10* is LOW.
When sending extended commands, the larger 10-bit character
size enlarges the extended command space to 1024 (2
possible commands codes.
Asynchronous Pre-encoded
In Asynchronous pre-encoded modes, the Transmit FIFO is
enabled and the Encoder is disabled (FIFOBYP* is HIGH and
ENCBYP* is LOW). This means that all words clocked into the
input register are written to the Transmit FIFO before being sent
to the Serializer. The Serializer operates synchronous to
REFCLK to generate the serial data bit-clock. SPDSEL and
RANGESEL determine whether REFCLK is multiplied by 10, 5
or 2.5 (if BYTE8/10* is HIGH) or 3, 6 or 12 (if BYTE8/10* is LOW).
In this mode the TXINT and TXHALT* inputs are used as part of
the 10-bit input character. TXSVS, TXSOC and TXSTOP* are
still available.
These modes are usually used for products containing external
encoders or scramblers, that must meet specific protocol
requirements. The host system must assert TXEN* and provide
new data at every rising edge of TXCLK to maintain the data
stream (without overfilling the Transmit FIFO). If the Transmit
FIFO ever goes empty, the Serializer is loaded with an alter-
nating disparity string of C5.0 (K28.5) sync characters (when
BYTE8/10* is HIGH) or the bit pattern 0110000100011 (when
BYTE8/10* is LOW).
This insertion can be an issue for some system implementations.
If the remote receiver is configured to decode 8B/10B coded
characters, it will probably detect running disparity errors
because the bypassed Encoder is not able to track the running
disparity of the previously transmitted character. However, since
these pre-encoded modes are generally used with alternate
forms of scrambling or encoding, for these applications this
disparity is not generally an issue.
To maintain a data stream without adding these C5.0 SYNC
codes, it is necessary that the Transmit FIFO be loaded at the
same speed or faster than the rate that data is read from that
FIFO.
CY7C924ADX HOTLink Receive-Path
Operating Mode Descriptions
The HOTLink Receiver can be configured into several operating
modes, each providing different capabilities and fitting different
reception needs. These modes are selected using the
FIFOBYP*,
Document #: 38-02008 Rev. *G
ENBYP*
and
BYTE8/10*
inputs
on
the
10
)
CY7C924ADX Transceiver. These modes can be reduced to five
primary classes:
■
■
■
■
■
In all these modes, serial data is received at one of the differential
line receiver inputs and routed to the Deserializer and Framer.
The PLL in the clock and data recovery block is used to extract
a bit-rate clock from the transitions in the data stream, and uses
that clock to capture bits from the serial stream. These bits are
passed to the Deserializer where they are formed into 10- or
12-bit characters.
To align the incoming bit stream to the proper character bound-
aries, the Framer must be enabled by asserting RFEN HIGH.
The Framer logic-block checks the incoming bit stream for the
unique pattern that defines the character boundaries. This logic
filter looks for the ANSI X3.230 symbol defined as a “Special
Character Comma” (K28.5 or C5.0). Once a K28.5 is found, the
Framer captures the offset of the data stream from the present
character boundaries, and resets the boundary to reflect this new
offset, thus framing the data to the correct character boundaries.
Since noise induced errors can cause the incoming data to be
corrupted, and since many combinations of corrupt and legal
data can create and aliased K28.5, the framer may also be
disabled by setting RFEN LOW.
An option exists in the framer to require multiple K28.5
characters, meeting specific criteria, before the character bound-
aries are reset. This multi-byte mode of the Framer is enabled by
keeping RFEN asserted HIGH for greater than 2048 character
clock cycles. For multi-byte framing, the receiver must find a pair
of K28.5 characters, both on identical 10-bit boundaries, within
a 5-character span (50 bits) before it shifts its framing bound-
aries. This option greatly reduces the probability of framing to
aliased K28.5 characters while still allowing many links to
maintain synchronization.
Synchronous Decoded
In these modes, the Receive FIFO is bypassed, while the 10B/8B
Decoder is enabled (FIFOBYP* is LOW and ENCBYP* is HIGH).
Framed characters output from the Deserializer are decoded,
and passed direct to the Receive Output Register. The Deseri-
alizer operates synchronous to the recovered bit-clock, which is
divided by 10 generate the output RXCLK clock. In this mode the
RXRST* input is not interpreted and may be biased either HIGH
or LOW.
These modes are usually used for products that must meet
specific protocol requirements. New decoded characters are
provided at the RXDATA outputs once every rising edge of
RXCLK. When RXEMPTY* is deasserted along with the data, it
indicates that a valid character (as selected by RXMODE[1:0]) is
present at the RXDATA outputs. When asserted it indicates that
a C5.0 (K28.5) not kept by the current RXMODE[1:0] setting is
present on the RXDATA output bus. Because the decoder is
enabled, all received characters are checked for compliance to
the 8B/10B decoding rules.
Synchronous Decoded
Synchronous Undecoded
Asynchronous Decoded
Asynchronous Byte-packed
Asynchronous Undecoded.
CY7C924ADX
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