VSC8601XKN Vitesse Semiconductor Corp, VSC8601XKN Datasheet - Page 10
![IC PHY 10/100/1000 64-EP-LQFP](/photos/6/86/68666/64-lqfp_exposed_pad__64-elqfp__64-hlqfp_sml.jpg)
VSC8601XKN
Manufacturer Part Number
VSC8601XKN
Description
IC PHY 10/100/1000 64-EP-LQFP
Manufacturer
Vitesse Semiconductor Corp
Type
PHY Transceiverr
Specifications of VSC8601XKN
Number Of Drivers/receivers
1/1
Protocol
Gigabit Ethernet
Voltage - Supply
2.5V, 3.3V
Mounting Type
Surface Mount
Package / Case
64-LQFP Exposed Pad, 64-eLQFP, 64-HLQFP
Case
TQFP
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
907-1028
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
VSC8601XKN
Manufacturer:
KYOCERA/AVX
Quantity:
20 000
Company:
Part Number:
VSC8601XKN
Manufacturer:
VITESSE
Quantity:
1 235
Company:
Part Number:
VSC8601XKN
Manufacturer:
Vitesse Semiconductor Corporation
Quantity:
10 000
Part Number:
VSC8601XKN
Manufacturer:
VITESSE
Quantity:
20 000
Revision 2.2
Revision 4.1
September 2009
•
•
•
•
•
•
Revision 2.2 of this datasheet was published in July 2006. The following is a summary
of the changes implemented in the datasheet:
•
•
•
•
•
•
•
register 28E.13:12 set to 10 or 11. In the second set, the minimum is 40% and the
maximum is 60% and the condition is: register 28E.13:12 set to 00 or 01.
In the AC characteristics for RGMII compensated, all of the setup and hold times
were modified from 0 ns maximum to 3 ns maximum.
In the description of pin MDIO, the type was corrected from open drain (OD) to
input and output (I/O).
The PLLMODE pin description was updated with additional clocking information. If a
crystal or an external 25 MHz clock is used, PLLMODE must be pulled low. If an
external 125 MHz clock is used, PLLMODE must be pulled high.
A design guideline was added regarding writes from the serial management
interface (SMI) after a software reset.
A design guideline was added regarding delays in the link-up process while in the
forced 100BASE-TX mode with the automatic MDI/MDI-X detection feature enabled.
The following design guidelines were removed, because they no longer apply to the
device: Remote Fault Status; DSP Optimization Script Required; Default Port Type
Incorrect; and Core 1.2 V Supply Needs to Meet Specific Range.
In the inline powered Ethernet switch diagram, a reference to “SGMII interface”
was corrected to “RGMII interface.”
In the description of CRC counters, the CRC good counter’s highest value was
corrected from 10,000 to 9,999 packets, after which the counter clears.
The device revision number definition was updated from 0000 to 0001 in the
identifier 2 register (address 3) and the JTAG device identification.
In the DC Characteristics for V
leakage (I
(I
were changed from –10 µA minimum and 10 µA maximum to –36 µA minimum and
36 µA maximum.
In the DC Characteristics for V
(I
the same condition (internal resistor included). Specifically, the values were
changed from –10 µA minimum and 10 µA maximum to –25 µA minimum and
25 µA maximum.
In the DC characteristics for V
voltage parameter (V
corrected to the condition I
For all the current consumption specifications with the on-chip switching regulator
enabled, the specification values for I
ILEAK
OLEAK
) with the same condition (internal resistor included). Specifically, the values
) was changed to match the same values as the input leakage (I
OLEAK
) was changed to match the same values as the input leakage
OH
) incorrectly stated I
OH
DDIOMAC
= –1.0 mA.
DD33
DDIOMAC
, V
VDD12
DDIOMAC
or V
or V
DDIOMICRO
DDIOMICRO
and I
OH
, or V
= 1.0 mA as a condition. It is now
VDD12A
DDIOMICRO
at 2.5 V, the output high
at 2.5 V, the output leakage
were removed because
at 3.3 V, the output
VSC8601 Datasheet
Revision History
ILEAK
Page 10
) with