PIC18F442-I/PT Microchip Technology Inc., PIC18F442-I/PT Datasheet - Page 116

• Manufacturer Part Number: PIC18F442-I/PT
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-TQFP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F442-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18FXX2
13.1
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The Operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
FIGURE 13-1:
FIGURE 13-2:
DS39564C-page 114
Set TMR3IF Flag bit
on Overflow
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1OSO/
T13CKI
T1OSI
Timer3 Operation
Data Bus<7:0>
Write TMR3L
Read TMR3L
T1OSO/
T13CKI
T1OSI
TMR3IF
Overflow
Interrupt
Flag bit
T1OSC
TIMER3 BLOCK DIAGRAM
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
8
High Byte
TMR3H
Timer3
8
To Timer1 Clock Input
TMR3H
T1OSC
Enable
Oscillator
T1OSCEN
8
TMR3
(1)
TMR3L
8
Oscillator
Enable
T1OSCEN
TMR3L
CLR
(1)
CLR
(3)
Internal
Clock
F
OSC
F
Internal
Clock
/4
OSC
TMR3ON
On/Off
TMR3CS
/4
TMR3ON
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored, and the pins are read as ‘0’.
Timer3 also has an internal “RESET input”. This RESET
can be generated by the CCP module (Section 14.0).
CCP Special Trigger
T3CCPx
On/Off
1
0
TMR3CS
1
0
T3CKPS1:T3CKPS0
T3CCPx
CCP Special Trigger
T3SYNC
T3CKPS1:T3CKPS0
Prescaler
1, 2, 4, 8
T3SYNC
0
1
Prescaler
1, 2, 4, 8
2
0
1
2
© 2006 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
SLEEP Input
Synchronized
Clock Input
Synchronize
SLEEP Input
det
det