PIC18F442-I/PT Microchip Technology Inc., PIC18F442-I/PT Datasheet - Page 180

• Manufacturer Part Number: PIC18F442-I/PT
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-TQFP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F442-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18FXX2
16.3.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
TABLE 16-9:
FIGURE 16-8:
DS39564C-page 178
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
Name
RC7/RX/DT pin
RC6/TX/CK pin
Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
Note:
(Interrupt)
CREN bit
Write to
bit SREN
SREN bit
RCIF bit
RXREG
by
Read
USART SYNCHRONOUS MASTER
RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
PSPIP
Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.
SPEN
CSRC
GIEH
Bit 7
GIE/
setting
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
(1)
(1)
(1)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'0'
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
either
TMR0IE INT0IE
SREN
TXEN
RCIF
RCIE
RCIP
enable
Bit 5
bit0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CREN ADDEN
SYNC
bit1
bit
TXIE
TXIP
Bit 4
TXIF
SREN
SSPIF
SSPIE
SSPIP
bit2
RBIE
Bit 3
—
TMR0IF INT0IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
bit3
BRGH
FERR
Bit 2
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit4
OERR
TRMT
Bit 1
bit5
RX9D
TX9D
RBIF
Bit 0
© 2006 Microchip Technology Inc.
bit6
0000 000x 0000 000u
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on
bit7
Q1 Q2 Q3 Q4
All Other
Value on
RESETS
'0'