PIC18F442-I/PT Microchip Technology Inc., PIC18F442-I/PT Datasheet - Page 178
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PIC18F442-I/PT
Manufacturer Part Number
PIC18F442-I/PT
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-TQFP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F442-IPT.pdf
(332 pages)
Specifications of PIC18F442-I/PT
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F442-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18FXX2
16.3
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
16.3.1
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one T
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
TABLE 16-8:
DS39564C-page 176
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
Name
USART Synchronous Master
Mode
Shaded cells are not used for Synchronous Master Transmission.
clear.
PSPIF
PSPIE
PSPIP
USART Transmit Register
USART SYNCHRONOUS MASTER
TRANSMISSION
CSRC
SPEN
GIEH
Bit 7
GIE/
CYCLE
(1)
(1)
(1)
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
), the TXREG is empty and inter-
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
TMR0IE INT0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
CREN ADDEN
SYNC
Bit 4
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
—
TMR0IF
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
BRGH
FERR
Bit 2
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE, and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit, which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
To set up a Synchronous Master Transmission:
1.
2.
3.
4.
5.
6.
7.
Note:
Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
INT0IF
OERR
TRMT
Bit 1
TXIF is not cleared immediately upon load-
ing data into the transmit buffer TXREG.
The flag bit becomes valid in the second
instruction
instruction.
RX9D
TX9D
RBIF
Bit 0
© 2006 Microchip Technology Inc.
cycle
0000 000x
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
following
0000 000u
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 -010
0000 0000
All Other
Value on
RESETS
the
load
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