PIC18F442-I/PT Microchip Technology Inc., PIC18F442-I/PT Datasheet - Page 117
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PIC18F442-I/PT
Manufacturer Part Number
PIC18F442-I/PT
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-TQFP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F442-IPT.pdf
(332 pages)
Specifications of PIC18F442-I/PT
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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Quantity
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Part Number:
PIC18F442-I/PT
Manufacturer:
Microchip Technology
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13.2
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low
power oscillator rated up to 200 KHz. See Section 11.0
for further details.
13.3
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 Interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 interrupt enable bit, TMR3IE
(PIE2<1>).
TABLE 13-1:
© 2006 Microchip Technology Inc.
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Name
Timer1 Oscillator
Timer3 Interrupt
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
GIEH
RD16
RD16
Bit 7
GIE/
—
—
—
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3CCP2
PEIE/
Bit 6
GIEL
—
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
T3CKPS1 T3CKPS0
TMR0IE
Bit 5
—
—
—
INT0IE
EEIF
EEIE
EEIP
Bit 4
T3CCP1
BCLIE
BCLIP
BCLIF
RBIE
Bit 3
T3SYNC
TMR0IF
13.4
If the CCP module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this RESET operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L registers pair
effectively becomes the period register for Timer3.
LVDIE
LVDIP
LVDIF
Bit 2
Note:
Resetting Timer3 Using a CCP
Trigger Output
TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR3CS TMR3ON 0000 0000 uuuu uuuu
TMR3IF
TMR3IE
TMR3IP
INT0IF
The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
Bit 1
CCP2IE
CCP2IP
CCP2IF
RBIF
Bit 0
PIC18FXX2
0000 000x 0000 000u
---0 0000 ---0 0000
---0 0000 ---0 0000
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOR
Value on
DS39564C-page 115
All Other
Value on
RESETS
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