PIC18F442-I/PT Microchip Technology Inc., PIC18F442-I/PT Datasheet - Page 68
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PIC18F442-I/PT
Manufacturer Part Number
PIC18F442-I/PT
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-TQFP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F442-IPT.pdf
(332 pages)
Specifications of PIC18F442-I/PT
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F442-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18FXX2
REGISTER 6-1:
DS39564C-page 66
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER (ADDRESS FA6h)
bit 7
EEPGD: FLASH Program or Data EEPROM Memory Select bit
1 = Access FLASH Program memory
0 = Access Data EEPROM memory
CFGS: FLASH Program/Data EE or Configuration Select bit
1 = Access Configuration or Calibration registers
0 = Access FLASH Program or Data EEPROM memory
Unimplemented: Read as '0'
FREE: FLASH Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: FLASH Program/Data EE Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
Note:
WREN: FLASH Program/Data EE Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
- n = Value at POR
EEPGD
R/W-x
(cleared by completion of erase operation)
(any MCLR or any WDT Reset during self-timed programming in normal operation)
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing
of the error condition.
R/W-x
CFGS
U-0
—
W = Writable bit
’1’ = Bit is set
R/W-0
FREE
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
WREN
R/W-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
R/S-0
WR
R/S-0
RD
bit 0
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