DS2148T+ Maxim Integrated Products, DS2148T+ Datasheet - Page 29

• Manufacturer Part Number: DS2148T+
• Description: IC LIU E1/T1/J1 5V 44-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS2148T+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4-1. MCLK Selection
CCR2 (01H): COMMON CONTROL REGISTER 2
(MSB)
2.048MHz
2.048MHz
1.544MHz
P25S
SYMBOL
MCLK
RHBE
THBE
SCLD
CLDS
RCES
TCES
P25S
-
N/A
(CCR1.3)
JAMUX
POSITION
CCR2.7
CCR2.6
CCR2.5
CCR2.4
CCR2.3
CCR2.2
CCR2.1
CCR2.0
0
1
0
SCLD
(CCR1.7)
DESCRIPTION
Pin 25 Select. Forced to logic 0 in hardware mode.
0 = toggles high during a Receive Carrier Loss condition
1 = toggles high if TCLK does not transition for at least 5µs.
Not Assigned. Should be set to zero when written to.
Short Circuit Limit Disable (ETS = 0). Controls the 50mA
(RMS) current limiter.
0 = enable 50mA current limiter
1 = disable 50mA current limiter
Custom Line Driver Select. Setting this bit to a one will
redefine the operation of the transmit line driver. When this bit
is set to a one and CCR4.5 = CCR4.6 = CCR4.7 = 0, then the
device will generate a square wave at the TTIP and TRING
outputs instead of a normal waveform. When this bit is set to a
one and CCR4.5 = CCR4.6 = CCR4.7 ≠ 0, then the device will
force TTIP and TRING outputs to become open drain drivers
instead of their normal push-pull operation. This bit should be
set to zero for normal operation of the device. Contact the
factory for more details on how to use this bit.
Receive HDB3/B8ZS Enable. See
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
Transmit HDB3/B8ZS Enable. See
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
Transmit Clock Edge Select. Selects which TCLK edge to
sample TPOS and TNEG. See
0 = sample TPOS and TNEG on falling edge of TCLK
1 = sample TPOS and TNEG on rising edge of TCLK
Receive Clock Edge Select. Selects which RCLK edge to
update RPOS and RNEG. See
0 = update RPOS and RNEG on rising edge of RCLK
1 = update RPOS and RNEG on falling edge of RCLK
CLDS
ETS
0
1
1
29 of 73
RHBE
THBE
Figure
Figure
Figure
Figure
1-2.
1-3.
TCES
1-2.
1-3.
(LSB)
RCES