DS2148T+ Maxim Integrated Products, DS2148T+ Datasheet - Page 30

• Manufacturer Part Number: DS2148T+
• Description: IC LIU E1/T1/J1 5V 44-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS2148T+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CCR3 (02H): COMMON CONTROL REGISTER 3
SYMBOL
(MSB)
TUA1
TPRBSE
ATUA1
LIRST
TAOZ
TUA1
TLCE
IBPV
IBE
ATUA1
POSITION
CCR3.7
CCR3.6
CCR3.5
CCR3.4
CCR3.3
CCR3.2
CCR3.1
CCR3.0
TAOZ
DESCRIPTION
Transmit Unframed All Ones. The polarity of this bit is set such
that the device will transmit an all ones pattern on power-up or
device reset. This bit must be set to a one to allow the device to
transmit data. The transmission of this data pattern is always timed
off of the JACLK (See
0 = transmit all ones at TTIP and TRING
1 = transmit data normally
Automatic Transmit Unframed All Ones. Automatically transmit
an unframed all ones pattern at TTIP and TRING during a receive
carrier loss (RCL) condition or a receive all ones condition.
0 = disabled
1 = enabled
Transmit Alternate Ones and Zeros. Transmit a …101010…
pattern at TTIP and TRING. The transmission of this data pattern is
always timed off of TCLK (See
0 = disabled
1 = enabled
Transmit PRBS Enable. Transmit a 2
PRBS at TTIP and TRING. See
0 = disabled
1 = enabled
Transmit Loop Code Enable. Enables the transmit side to
transmit the loop up code in the Transmit Code Definition registers
(TCD1 and TCD2). See Section
0 = disabled
1 = enabled
Line Interface Reset. Setting this bit from a zero to a one will
initiate an internal reset that resets the clock recovery state machine
and re-centers the jitter attenuator. Normally this bit is only toggled
on power-up. Must be cleared and set again for a subsequent reset.
Insert BPV. A 0 to 1 transition on this bit will cause a single
Bipolar Violation (BPV) to be inserted into the transmit data
stream. Once this bit has been toggled from a 0 to a 1, the device
waits for the next occurrence of three consecutive ones to insert the
BPV. This bit must be cleared and set again for a subsequent error
to be inserted. See
Insert Bit Error. A 0 to 1 transition on this bit will cause a single
logic error to be inserted into the transmit data stream. This bit
must be cleared and set again for a subsequent error to be inserted.
See
TPRBSE
Figure
1-3.
30 of 73
TLCE
Figure
Figure
1-3.
1-1).
LIRST
Figure
Figure
4
and
Figure 1-3
15
1-1).
1-3.
- 1 (E1) or a 2
IBPV
for details.
20
- 1 (T1)
(LSB)
IBE