IDT82V2044EPFG8 IDT, Integrated Device Technology Inc, IDT82V2044EPFG8 Datasheet - Page 22
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IDT82V2044EPFG8
Manufacturer Part Number
IDT82V2044EPFG8
Description
IC LINE INTERFC UNIT 4CH 128TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Line Interface Units (LIUs)r
Datasheet
1.IDT82V2044EPFG8.pdf
(73 pages)
Specifications of IDT82V2044EPFG8
Protocol
E1
Voltage - Supply
3.13 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
800-1863-2
82V2044EPFG8
82V2044EPFG8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V2044EPFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.4
uator can be deployed in the transmit path or the receive path, and can also
be disabled. This is selected by the JACF[1:0] bits (JACF, 01H...).
3.4.1
Figure-12. The FIFO is used as a pool to buffer the jittered input data, then
the data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits
(JACF, 01H...). Consequently, the constant delay of the Jitter Attenuator
will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but
at the expense of increasing data latency time.
There is one Jitter Attenuator in each channel of the LIU. The Jitter Atten-
The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in
Jittered Clock
Jittered Data
JITTER ATTENUATOR
JITTER ATTENUATION FUNCTION DESCRIPTION
Figure-12 Jitter Attenuator
W
32/64/128
FIFO
DPLL
MCLK
R
De-jittered Data
De-jittered Clock
RDn/RDPn
RDNn
RCLKn
22
6.8 Hz, as selected by the JABW bit (JACF, 01H...). In T1/J1 applications,
the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected
by the JABW bit (JACF, 01H...). The lower the Corner Frequency is, the
longer time is needed to achieve synchronization.
will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 17H...).
If the incoming data moves slower than the outgoing data, the FIFO will
underflow. This underflow is captured by the
For some applications that are sensitive to data corruption, the JA limit
mode can be enabled by setting JA_LIMIT bit (JACF, 01H...) to ‘1’. In the
JA limit mode, the speed of the outgoing data will be adjusted automatically
when the FIFO is close to its full or emptiness. The criteria of starting speed
adjustment are shown in Table-12. The JA limit mode can reduce the pos-
sibility of FIFO overflow and underflow, but the quality of jitter attenuation
is deteriorated.
3.4.2
ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/
13, AT&T TR62411 specifications. Details of the Jitter Attenuator perfor-
mance is shown in
Characteristics.
Table-12 Criteria of Starting Speed Adjustment
In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or
When the incoming data moves faster than the outgoing data, the FIFO
The performance of the Jitter Attenuator in the IDT82V2044E meets the
FIFO Depth
128 Bits
32 Bits
64 Bits
JITTER ATTENUATOR PERFORMANCE
Table-64 Jitter Tolerance
Criteria for Adjusting Data Outgoing Speed
2 bits close to its full or emptiness
3 bits close to its full or emptiness
4 bits close to its full or emptiness
TEMPERATURE RANGES
and
JAUD_IS
Table-65 Jitter Attenuator
bit (INTS1, 17H...).
INDUSTRIAL