PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 253
PIC18F2455-I/SP
Manufacturer Part Number
PIC18F2455-I/SP
Description
Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2455-ISP.pdf
(320 pages)
Specifications of PIC18F2455-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
23
Interface
I2C/SPI/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
24K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2455-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If CNT
PC
If CNT
PC
No
No
No
Q1
Q1
Q1
register ‘f’
operation
operation
operation
Test f, Skip if 0
TSTFSZ f {,a}
0
a
skip if f = 0
None
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
=
=
=
=
f
[0,1]
255
by a 2-word instruction.
Address (HERE)
00h,
Address (ZERO)
00h,
Address (NZERO)
TSTFSZ
:
:
011a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
95 (5Fh). See
CNT, 1
ffff
Advance Information
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
PIC18F2450/4450
=
=
literal ‘k’
Exclusive OR Literal with W
XORLW k
0
(W) .XOR. k
N, Z
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
1
1
XORLW
Read
Q2
0000
B5h
1Ah
k
255
0AFh
1010
Process
Data
W
Q3
DS39760A-page 251
kkkk
Write to W
Q4
kkkk
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