PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 310

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2450/4450
Code Examples
Code Protection ............................................................... 189
COMF ............................................................................... 228
Compare (CCP Module) ................................................... 125
Configuration Bits ............................................................. 190
Configuration Register Protection .................................... 209
Context Saving During Interrupts ....................................... 97
Conversion Considerations .............................................. 304
CPFSEQ .......................................................................... 228
CPFSGT ........................................................................... 229
CPFSLT ........................................................................... 229
Crystal Oscillator/Ceramic Resonator ................................ 25
Customer Change Notification Service ............................ 315
Customer Notification Service .......................................... 315
Customer Support ............................................................ 315
D
Data Addressing Modes ..................................................... 67
Data Memory ...................................................................... 59
DAW ................................................................................. 230
DC and AC Characteristics
DS39760A-page 308
16 x 16 Signed Multiply Routine ................................ 84
16 x 16 Unsigned Multiply Routine ............................ 84
8 x 8 Signed Multiply Routine .................................... 83
8 x 8 Unsigned Multiply Routine ................................ 83
Changing Between Capture Prescalers ................... 124
Computed GOTO Using an Offset Value ................... 56
Erasing a Flash Program Memory Row ..................... 78
Fast Register Stack .................................................... 56
How to Clear RAM (Bank 1) Using
Implementing a Real-Time Clock Using
Initializing PORTA ...................................................... 99
Initializing PORTB .................................................... 101
Initializing PORTC .................................................... 104
Initializing PORTD .................................................... 107
Initializing PORTE .................................................... 109
Reading a Flash Program Memory Word .................. 77
Saving STATUS, WREG and
Writing to Flash Program Memory ....................... 80–81
Associated Registers ............................................... 126
CCP1 Pin Configuration ........................................... 125
CCPR1 Register ...................................................... 125
Software Interrupt .................................................... 125
Special Event Trigger ............................................... 125
Timer1 Mode Selection ............................................ 125
Comparing Addressing Modes with
Direct .......................................................................... 67
Indexed Literal Offset ................................................. 70
Indirect ....................................................................... 67
Inherent and Literal .................................................... 67
Access Bank .............................................................. 61
and the Extended Instruction Set ............................... 70
Bank Select Register (BSR) ....................................... 59
General Purpose Registers ........................................ 61
Map for PIC18F2450/4450 Devices ........................... 60
Special Function Registers ........................................ 62
USB RAM ................................................................... 59
Graphs and Tables .................................................. 293
Indirect Addressing ............................................ 67
a Timer1 Interrupt Service ............................... 119
BSR Registers in RAM ....................................... 97
the Extended Instruction Set Enabled ................ 71
BSR Operation ................................................... 72
Instructions Affected .......................................... 70
Mapping the Access Bank ................................. 72
Map .................................................................... 62
Advance Information
DC Characteristics ........................................................... 276
DCFSNZ .......................................................................... 231
DECF ............................................................................... 230
DECFSZ .......................................................................... 231
Dedicated ICD/ICSP Port ................................................ 209
Development Support ...................................................... 261
Device Differences ........................................................... 303
Device Overview .................................................................. 7
Direct Addressing .............................................................. 68
E
Effect on Standard PIC MCU Instructions ....................... 258
Electrical Characteristics ................................................. 265
Enhanced Universal Synchronous Receiver
Equations
Errata ................................................................................... 6
EUSART
Extended Instruction Set .................................................. 253
External Clock Input ........................................................... 26
Power-Down and Supply Current ............................ 268
Supply Voltage ........................................................ 267
Features (table) ........................................................... 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Transmitter (USART). See EUSART.
A/D Acquisition Time ............................................... 178
A/D Minimum Charging Time ................................... 178
Calculating the Minimum Required
Asynchronous Mode ................................................ 162
Baud Rate Generator (BRG) ................................... 157
Synchronous Master Mode ...................................... 168
Synchronous Slave Mode ........................................ 171
ADDFSR .................................................................. 254
ADDULNK ................................................................ 254
and Using MPLAB IDE Tools ................................... 260
CALLW .................................................................... 255
Considerations for Use ............................................ 258
MOVSF .................................................................... 255
MOVSS .................................................................... 256
PUSHL ..................................................................... 256
SUBFSR .................................................................. 257
SUBULNK ................................................................ 257
Syntax ...................................................................... 253
A/D Acquisition Time ....................................... 178
Associated Registers, Receive ........................ 165
Associated Registers, Transmit ....................... 163
Auto-Wake-up on Sync Break ......................... 166
Break Character Sequence ............................. 167
Receiver .......................................................... 164
Setting Up 9-Bit Mode with Address Detect .... 164
Transmitter ...................................................... 162
Associated Registers ....................................... 157
Auto-Baud Rate Detect .................................... 160
Baud Rate Error, Calculating ........................... 157
Baud Rates, Asynchronous Modes ................. 158
High Baud Rate Select (BRGH Bit) ................. 157
Operation in Power-Managed Modes .............. 157
Sampling .......................................................... 157
Associated Registers, Receive ........................ 170
Associated Registers, Transmit ....................... 169
Reception ........................................................ 170
Transmission ................................................... 168
Associated Registers, Receive ........................ 172
Associated Registers, Transmit ....................... 171
Reception ........................................................ 172
Transmission ................................................... 171
© 2006 Microchip Technology Inc.