PIC16F628-20I/P Microchip Technology Inc., PIC16F628-20I/P Datasheet - Page 51
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PIC16F628-20I/P
Manufacturer Part Number
PIC16F628-20I/P
Description
18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F628-20IP.pdf
(170 pages)
Specifications of PIC16F628-20I/P
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
16
Interface
SCI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
224 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F628-20I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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7.4
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 7-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 7-1:
TABLE 7-2:
2003 Microchip Technology Inc.
Note 1: These values are for design guidance only.
0Bh/8Bh/
10Bh/18Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend:
Address
Osc Type
LP
Timer1 Oscillator
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Consult AN826 (DS00826A) for further
information on Crystal/Capacitor Selection.
INTCON
PIR1
PIE1
TMR1L
TMR1H
T1CON
Name
100 kHz
200 kHz
32 kHz
Freq
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Bit 7
EEIF
EEIE
GIE
—
Bit 6
CMIE
PEIE
CMIF
33 pF
15 pF
15 pF
—
C1
T1CKPS1
Bit 5
RCIF
RCIE
T0IE
33 pF
15 pF
15 pF
C2
T1CKPS0
Bit 4
INTE
TXIE
TXIF
Preliminary
T1OSCEN
Bit 3
RBIE
—
—
7.5
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPRxH:CCPRxL
registers pair effectively becomes the period register
for Timer1.
7.6
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other RESET except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
7.7
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Note:
T1SYNC
CCP1IF
CCP1IE
Bit 2
T0IF
Resetting Timer1 Using a CCP
Trigger Output
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
Timer1 Prescaler
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR1CS
TMR2IF
TMR2IE
Bit 1
INTF
TMR1ON
TMR1IF
TMR1IE
Bit 0
RBIF
PIC16F62X
0000 000x
0000 -000
0000 -000
xxxx xxxx
xxxx xxxx
--00 0000
Value on
POR
DS40300C-page 49
0000 000u
0000 -000
0000 -000
uuuu uuuu
uuuu uuuu
--uu uuuu
Value on
RESETS
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