PIC16F628-20I/P Microchip Technology Inc., PIC16F628-20I/P Datasheet - Page 94
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PIC16F628-20I/P
Manufacturer Part Number
PIC16F628-20I/P
Description
18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F628-20IP.pdf
(170 pages)
Specifications of PIC16F628-20I/P
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
16
Interface
SCI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
224 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F628-20I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC16F62X
REGISTER 14-1: CONFIGURATION WORD
DS40300C-page 92
bit 13
bit 13-10:
bit 9:
bit 8:
bit 7:
bit 6:
bit 5:
bit 3:
bit 2:
bit 4, 1-0:
Legend
R = Readable bit
-n = Value at POR
CP1
CP0
CP1:CP0: Code Protection bits
Code protection for 2K program memory
11 = Program memory code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFhcode protected
Code protection for 1K program memory
11 = Program memory code protection off
10 = Program memory code protection off
01 = 0200h-03FFh code protected
00 = 0000h-03FFh code protected
Unimplemented: Read as ‘0’
CPD: Data Code Protection bit
1 = Data memory code protection off
0 = Data memory code protected
LVP: Low Voltage Programming Enable
1 = RB4/PGM pin has PGM function, low voltage programming enabled
0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming
BODEN: Brown-out Detect Reset Enable bit
1 = BOD Reset enabled
0 = BOD Reset disabled
MCLRE: RA5/MCLR pin function select
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital Input, MCLR internally tied to V
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC2:FOSC0: Oscillator Selection bits
111 = ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
110 = ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
101 = INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note
1:
2:
3:
4:
CP1
Enabling Brown-out Detect Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Detect Reset is enabled.
All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
The entire data EEPROM will be erased when the code protection is turned off.
When MCLR is asserted in INTRC or ER mode, the internal clock oscillator is disabled.
CP0
W = Writable bit
1 = bit is set
(3)
—
(2)
(1)
(4)
CPD
(1)
Preliminary
LVP
BODEN
U = Unimplemented bit, read as ‘0’
0 = bit is cleared
DD
MCLRE
FOSC2
PWRTE
2003 Microchip Technology Inc.
x = bit is unknown
WDTE
F0SC1
F0SC0
bit 0
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