PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 128

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
13.3
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the TMR1 register value.
When a match occurs, the CCPx pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
13.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 13-2:
DS39682B-page 126
I/O latch)
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP2CON register will force
the RB3 or RC1 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTB or
PORTC I/O data latch.
CCPR2H
CCPR1H
COMPARE MODE OPERATION BLOCK DIAGRAM
TMR1H
Comparator
Comparator
CCPR2L
CCPR1L
TMR1L
Compare
Compare
Match
Match
Set CCP1IF
Preliminary
Set CCP2IF
(Timer1 Reset, A/D Trigger)
Special Event Trigger
Special Event Trigger
CCP1CON<3:0>
CCP2CON<3:0>
13.3.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
13.3.3
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled and the CCPxIE bit is set.
13.3.4
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCPxM3:CCPxM0 = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
(Timer1 Reset)
Output
Output
Logic
4
Logic
4
Compare
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
S
R
S
R
Special
Q
Q
© 2006 Microchip Technology Inc.
Output Enable
Output Enable
TRIS
TRIS
Event
CCP1 pin
CCP2 pin
Trigger
mode