PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 148

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
15.3.1
Each MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register 1 (SSPxCON1)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPxSR) – Not directly
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower 6 bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
REGISTER 15-1:
DS39682B-page 146
(SSPxBUF)
accessible
REGISTERS
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPxSTAT: MSSPx STATUS REGISTER (SPI™ MODE)
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
D/A: Data/Address bit
Used in I
P: Stop bit
Used in I
cleared.
S: Start bit
Used in I
R/W: Read/Write Information bit
Used in I
UA: Update Address bit
Used in I
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty
Legend:
R = Readable bit
-n = Value at POR
R/W-0
Note:
SMP
2
2
2
2
2
C mode only.
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
C mode only.
C mode only.
C mode only.
Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
R/W-0
CKE
W = Writable bit
‘1’ = Bit is set
D/A
Preliminary
R-0
R-0
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
transmission,
R-0
S
R/W
R-0
© 2006 Microchip Technology Inc.
the
x = Bit is unknown
SSPxBUF
R-0
UA
is
R-0
BF
bit 0
not