PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 343

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

APPENDIX A:
Revision A (March 2005)
Original data sheet for PIC18F45J10 family devices.
TABLE B-1:
© 2006 Microchip Technology Inc.
Operating Frequency
Supply Voltage
Operating Current
Program Memory Endurance
I/O Sink/Source at 25 mA
Input Voltage Tolerance on I/O pins
I/O
Pull-ups
Oscillator Options
Program Memory Retention
Programming Time (Normalized)
Programming Entry
Code Protection
Configuration Words
Start-up Time from Sleep
Power-up Timer
Data EEPROM
BOR
LVD
A/D Calibration
In-Circuit Emulation
TMR3
Second MSSP
Note 1:
2:
BOR is not available on PIC18LFXXJ10 devices.
Available on 40/44-pin devices only.
Characteristic
NOTABLE DIFFERENCES BETWEEN PIC18F4520 AND PIC18FXXXX FAMILIES
REVISION HISTORY
156 μs/byte (10 ms/64-byte block)
1,000 write/erase cycles (typical)
(EC, HS, fixed 32 kHz INTRC)
Low Voltage, Key Sequence
Single block, all or nothing
PORTB and PORTC only
Stored in last 4 words of
Program Memory space
5.5V on digital only pins
PIC18FXXXX Family
10 years (minimum)
40 MHz @ 2.15V
Preliminary
200 μs (typical)
Limited options
Simple BOR
Not available
Not available
Not available
Not available
Available
Always on
2.0V-3.6V
Required
PORTB
Low
32
PIC18F45J10 FAMILY
(2)
APPENDIX B:
Devices in the PIC18F45J10 family and PIC18F4520
families are very similar in their functions and feature
sets. However, there are some potentially important
differences
migrating an application across device families to
achieve a new design goal. These are summarized in
Table B-1. The areas of difference which could be a
major impact on migration are discussed in greater
detail later in this section.
(1)
which
100,000 write/erase cycles (typical)
More options (EC, HS, XT, LP, RC,
15.6 μs/byte (1 ms/64-byte block)
Multiple code protection blocks
Stored in Configuration Space,
should
MIGRATION
BETWEEN HIGH-END
DEVICE FAMILIES
PIC18F4520 Family
PLL, flexible INTRC)
Programmable BOR
40 years (minimum)
starting at 300000h
V
40 MHz @ 4.2V
DD
10 μs (typical)
V
Configurable
Not available
Not required
2.0V-5.5V
PP
on all I/O pins
Available
Available
Available
Available
be
All ports
PORTB
Lower
and LVP
36
DS39682B-page 341
considered
when