PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 326

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
TABLE 23-21: MASTER SSP I
DS39682B-page 324
100
101
102
103
90
91
106
107
92
109
110
D102
Legend: TBD = To Be Determined
Note 1:
Param.
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
Maximum pin capacitance = 10 pF for all I
A Fast mode I
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data
bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before
the SCLx line is released.
:
:
:
:
:
STA
DAT
STO
STA
DAT
Clock High Time 100 kHz mode
Clock Low Time 100 kHz mode
SDAx and SCLx
Rise Time
SDAx and SCLx
Fall Time
Start Condition
Setup Time
Start Condition
Hold Time
Data Input
Hold Time
Data Input
Setup Time
Stop Condition
Setup Time
Output Valid
from Clock
Bus Free Time
Bus Capacitive Loading
2
C bus device can be used in a Standard mode I
Characteristic
2
C™ BUS DATA REQUIREMENTS
400 kHz mode
1 MHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Preliminary
2
C™ pins.
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
OSC
OSC
OSC
OSC
OSC
OSC
20 + 0.1 C
20 + 0.1 C
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
TBD
TBD
TBD
Min
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
250
100
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
4.7
1.3
—
—
—
—
—
—
—
—
0
0
B
B
2
C bus system, but parameter #107 ≥ 250 ns
1000
3500
1000
Max
300
300
300
300
100
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
ns
© 2006 Microchip Technology Inc.
C
10 to 400 pF
C
10 to 400 pF
Only relevant for
Repeated Start
condition
clock pulse is generated
(Note 2)
Time the bus must be free
before a new transmission
can start
After this period, the first
B
B
is specified to be from
is specified to be from
Conditions