PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 61

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 5-2:
© 2006 Microchip Technology Inc.
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
TRISE
TRISD
TRISC
TRISB
TRISA
SSP2BUF
LATE
LATD
LATC
LATB
LATA
SSP2ADD
SSP2STAT
SSP2CON1
SSP2CON2
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note
File Name
(2)
(2)
(2)
(2)
(2)
(2)
1:
2:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
See Section 4.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.
These registers and/or bits are not implemented on 28-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
EEPROM Control Register 2 (not a physical register)
PORTD Data Direction Control Register
PORTC Data Direction Control Register
PORTB Data Direction Control Register
MSSP2 Receive Buffer/Transmit Register
PORTD Data Latch Register (Read and Write to Data Latch)
PORTC Data Latch Register (Read and Write to Data Latch)
PORTB Data Latch Register (Read and Write to Data Latch)
MSSP2 Address Register in I
PSPIP
PSPIF
PSPIE
OSCFIP
OSCFIF
OSCFIE
SSP2IP
SSP2IF
SSP2IE
WCOL
CSRC
GCEN
SPEN
Bit 7
SMP
RD7
RC7
RB7
IBF
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)
(2)
(2)
(2)
ACKSTAT
BCL2IP
BCL2IE
SSPOV
BCL2IF
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
OBF
CKE
RX9
RD6
RC6
RB6
TX9
—
—
—
—
—
—
PORTA Data Latch Register (Read and Write to Data Latch)
2
C™ Slave mode. MSSP2 Baud Rate Reload Register in I
TRISA5
SSPEN
ACKDT
TXEN
SREN
RCIP
RCIF
RCIE
IBOV
Bit 5
RD5
RC5
RB5
RA5
D/A
—
—
—
—
—
—
—
—
—
PSPMODE
ACKEN
SYNC
CREN
FREE
Bit 4
TXIP
TXIF
TXIE
CKP
RD4
RC4
RB4
—
—
—
—
—
—
—
—
—
—
P
Preliminary
WRERR
SENDB
ADDEN
BCL1IP
BCL1IE
SSP1IP
SSP1IF
SSP1IE
TRISA3
BCL1IF
SSPM3
RCEN
Bit 3
RD3
RC3
RB3
RA3
—
—
—
—
—
—
S
PIC18F45J10 FAMILY
PORTE Data Latch Register
(Read and Write to Data Latch)
CCP1IP
CCP1IE
CCP1IF
TRISE2
TRISA2
SSPM2
WREN
BRGH
RE2
FERR
Bit 2
PEN
RD2
RC2
R/W
RB2
RA2
—
—
—
—
—
—
(2)
‘
0
’
. Reset values are shown for 40/44-pin devices;
TMR2IP
TMR2IE
TMR2IF
TRISA1
TRISE1
SSPM1
OERR
RE1
TRMT
2
RSEN
Bit 1
RD1
RC1
C Master mode.
RB1
RA1
WR
UA
—
—
—
—
—
—
(2)
TMR1IP
TMR1IE
CCP2IP
CCP2IF
CCP2IE
TMR1IF
TRISE0
TRISA0
SSPM0
RE0
RX9D
TX9D
Bit 0
SEN
RD0
RC0
RB0
RA0
BF
—
—
—
—
(2)
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0010
0000 000x
0000 0000
---0 x00-
11-- ----
00-- ----
00-- ----
11-- 1--1
00-- 0--0
00-- 0--0
1111 1111
0000 0000
0000 0000
1111 -111
1111 1111
1111 1111
1111 1111
--1- 1111
xxxx xxxx
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--0- 0000
POR, BOR
DS39682B-page 59
Value on
on page:
46, 146,
46, 147,
Details
45, 192
45, 192
45, 199
45, 197
45, 188
45, 189
46, 107
46, 103
46, 100
46, 154
46, 106
46, 103
46, 100
46, 154
46, 158
46, 106
46, 103
46, 100
45, 68
45, 69
45, 89
45, 85
45, 87
45, 89
45, 85
45, 87
45, 88
45, 84
45, 86
46, 97
46, 94
46, 97
46, 94
46, 97
46, 94
156
157