PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 208

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
16.4
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CK pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
16.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 16-9:
DS39682B-page 206
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1:
Name
TSR register and transmit.
The second word will remain in the TXREG
register.
Flag bit, TXIF, will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit, TXIF, will now be
set.
If enable bit TXIE is set, the interrupt will wake the
chip from Sleep. If the global interrupt is enabled,
the program will branch to the interrupt vector.
The first word will immediately transfer to the
EUSART Synchronous
Slave Mode
These bits are not implemented on 28-pin devices and should be read as ‘0’.
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
(1)
(1)
(1)
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
—
Preliminary
INT0IE
CREN
SYNC
SCKP
TXIE
TXIP
Bit 4
TXIF
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
BRG16
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
RBIE
Bit 3
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
Bit 2
—
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
© 2006 Microchip Technology Inc.
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
on page
Values
Reset
43
45
45
45
45
45
45
45
45
45