PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 137
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PIC18F4431-I/P
Manufacturer Part Number
PIC18F4431-I/P
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4431-IP.pdf
(396 pages)
Specifications of PIC18F4431-I/P
A/d Inputs
9-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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11.1
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment, either on every
rising or falling edge of pin RC3/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the
rising edge.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
incrementing of Timer0 after synchronization.
11.2
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x....etc.) will clear the prescaler
count.
TABLE 11-1:
2003 Microchip Technology Inc.
TMR0L
TMR0H
INTCON
T0CON
TRISA
Legend:
Note 1: RA6 and RA7 are enabled as I/O pins depending on the Oscillator mode selected in Configuration Word 1H.
Note:
Name
Timer0 Operation
Prescaler
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Timer0 Module Low Byte Register
Timer0 Module High Byte Register
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
GIE/GIEH
TMR0ON
RA7
Bit 7
OSC
(1)
REGISTERS ASSOCIATED WITH TIMER0
). Also, there is a delay in the actual
PEIE/GIEL
T016BIT
RA6
Bit 6
(1)
PORTA Data Direction Register
TMR0IE
T0CS
Bit 5
PIC18F2331/2431/4331/4431
INT0IE
T0SE
Bit 4
Preliminary
RBIE
Bit 3
PSA
11.2.1
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on-the-fly” during program
execution).
11.3
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF bit. The interrupt can be masked by clearing
the TMR0IE bit. The TMR0IF bit must be cleared in
software by the Timer0 module interrupt service routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from Sleep mode, since
the timer requires clock cycles, even when T0CS is set.
11.4
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16 bits of Timer0 without
having to verify that the read of the high and low byte
were valid due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.
TMR0IF
T0PS2
Bit 2
Timer0 Interrupt
16-Bit Mode Timer Reads and
Writes
INT0IF
T0PS1
Bit 1
SWITCHING PRESCALER
ASSIGNMENT
T0PS0
Bit 0
RBIF
xxxx xxxx
0000 0000
0000 000x
1111 1111
1111 1111
POR, BOR
Value on
DS39616B-page 135
uuuu uuuu
0000 0000
0000 000u
1111 1111
1111 1111
Value on
all other
Resets
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