PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 237
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PIC18F4431-I/P
Manufacturer Part Number
PIC18F4431-I/P
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4431-IP.pdf
(396 pages)
Specifications of PIC18F4431-I/P
A/d Inputs
9-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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19.3.4
During Sleep mode, all clocks to the USART are sus-
pended. Because of this, the baud rate generator is
inactive and a proper byte reception cannot be per-
formed. The Auto-Wake-up feature allows the control-
ler to wake-up due to activity on the RX/DT line, while
the USART is operating in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit (BAUDCTL<1>). Once set, the typical receive
sequence on RX/DT is disabled, and the USART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event con-
sists of a high-to-low transition on the RX/DT line. (This
coincides with the start of a Sync Break or a Wake-up
Signal character for the LIN protocol.)
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 19-7), and asynchronously if the device is in
Sleep mode (Figure 19-8). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line, following the
wake-up event. At this point, the USART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
19.3.4.1
Since Auto-Wake-up functions by sensing rising edge
transitions on RX/DT, information with any state
changes before the Stop bit may signal a false end-of-
character and cause data or framing errors. To work
FIGURE 19-7:
FIGURE 19-8:
2003 Microchip Technology Inc.
RX/DT Line
Note 1:
Note 1:
RX/DT Line
WUE bit
WUE bit
OSC1
RCIF
OSC1
2:
RCIF
The USART remains in Idle while the WUE bit is set.
If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
The USART remains in Idle while the WUE bit is set.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Special Considerations Using
Auto-Wake-up
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit Set by User
Bit Set by User
Sleep Command Executed
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
PIC18F2331/2431/4331/4431
Preliminary
Q1
Sleep Ends
properly, therefore, the initial character in the
transmission must be all ‘0’s. This can be 00h (8 bytes)
for standard RS-232 devices, or 000h (12 bits) for LIN
bus.
Oscillator start-up time must also be considered, espe-
cially in applications using oscillators with longer start-
up intervals (i.e., LP, XT or HS/PLL mode). The sync
break (or wake-up signal) character must be of suffi-
cient length, and be followed by a sufficient interval, to
allow enough time for the selected oscillator to start
and provide proper initialization of the USART.
19.3.4.2
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
USART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCIF bit. The WUE bit
is cleared after this when a rising edge is seen on RX/
DT. The interrupt condition is then cleared by reading
the RCREG register. Ordinarily, the data in RCREG will
be dummy data and should be discarded.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Cleared due to User Read of RCREG
Cleared due to User Read of RCREG
Special Considerations Using the
WUE Bit
Note 1
DS39616B-page 235
Auto-Cleared
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