DSPIC30F4013-20I/PT Microchip Technology Inc., DSPIC30F4013-20I/PT Datasheet - Page 22

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: 16 BIT MCU/DSP 44LD 20MIPS 48 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F4013-20I/PT

• A/d Inputs: 13-Channels, 12-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: CAN, I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

ds
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The fol-
lowing instructions and data sizes are supported:
1.
2.
3.
4.
5.
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
DS70139D-page 20
DIVF
DIV.sd
DIV.s
DIV.ud
DIV.u
DIVF - 16/16 signed fractional divide
DIV.sd - 32/16 signed divide
DIV.ud - 32/16 unsigned divide
DIV.s - 16/16 signed divide
DIV.u - 16/16 unsigned divide
Instruction
PIC30F2011/2012/3012/3013
Divide Support
DIVIDE INSTRUCTIONS
Signed fractional divide: Wm/Wn
Signed divide: (Wm+1:Wm)/Wn
Signed divide: Wm/Wn
Unsigned divide: (Wm+1:Wm)/Wn
Unsigned divide: Wm/Wn
W0; Rem
W0; Rem
W0; Rem
W0; Rem
W0; Rem
W1
W1
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion, as shown in Table 2-1 (REPEAT executes the tar-
get instruction {operand value+1} times). The REPEAT
loop count must be setup for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
Function
Note:
W1
W1
W1
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
© 2006 Microchip Technology Inc.