DSPIC30F4013-20I/PT Microchip Technology Inc., DSPIC30F4013-20I/PT Datasheet - Page 38

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: 16 BIT MCU/DSP 44LD 20MIPS 48 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F4013-20I/PT

• A/d Inputs: 13-Channels, 12-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: CAN, I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

dsPIC30F2011/2012/3012/3013
3.2.2
The X data space is used by all instructions and sup-
ports all addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports Modulo Addressing for
all instructions, subject to Addressing mode restric-
tions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions dedi-
cates two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports Modulo Addressing for
automated circular buffers. Of course, all other instruc-
tions can access the Y data address space through the
X data path as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-8 and is not user pro-
grammable. Should an EA point to data outside its own
assigned address space, or to a location outside phys-
ical memory, an all zero word/byte is returned. For
example, although Y address space is visible by all
non-MAC instructions using any addressing mode, an
attempt by a MAC instruction to fetch data from that
space using W8 or W9 (X space pointers) returns
0x0000.
TABLE 3-2:
All Effective Addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
DS70139D-page 36
EA = an unimplemented address
W8 or W9 used to access Y data
space in a MAC instruction
W10 or W11 used to access X
data space in a MAC instruction
Attempted Operation
DATA SPACES
EFFECT OF INVALID
MEMORY ACCESSES
Data Returned
0x0000
0x0000
0x0000
3.2.3
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
To
PICmicro
memory usage efficiency, the dsPIC30F instruction set
supports both word and byte operations. Data is
aligned in data memory and registers as words, but all
data space EAs resolve to bytes. Data byte reads read
the complete word that contains the byte, using the LSb
of any EA to determine which byte to select. The
selected byte is placed onto the LSB of the X data path
(no byte accesses are possible from the Y data path as
the MAC class of instruction can only fetch words). That
is, data memory and registers are organized as two
parallel byte wide entities with shared (word) address
decode but separate write lines. Data byte writes only
write to the corresponding side of the array or register
which matches the byte address.
As a consequence of this byte accessibility, all Effective
Address calculations (including those generated by the
DSP operations which are restricted to word-sized
data) are internally scaled to step through word-aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode
[Ws++] results in a value of Ws + 1 for byte operations
and Ws + 2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. Should a mis-
aligned read or write be attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed, whereas if it
occurred on a write, the instruction is executed, but the
write does not occur. In either case, a trap is then exe-
cuted, allowing the system and/or user to examine the
machine state prior to execution of the address fault.
FIGURE 3-10:
0001
0003
0005
help
®
15
DATA SPACE WIDTH
DATA ALIGNMENT
maintain
MCU devices and improve data space
MSB
Byte 1
Byte 3
Byte 5
DATA ALIGNMENT
backward
© 2006 Microchip Technology Inc.
8 7
LSB
Byte 0
Byte 2
Byte 4
compatibility
0
0000
0002
0004
with