PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 186
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PIC18F46K80-I/P
Manufacturer Part Number
PIC18F46K80-I/P
Description
40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F46K80-I/P
A/d Inputs
11-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
1K Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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Price
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PIC18F66K80 FAMILY
TABLE 11-3:
TABLE 11-4:
DS39977C-page 186
RB5/T0CKI/T3CKI/
CCP5/KBI1
RB6/PGC/TX2/CK2/
KBI2
RB7/PGD/T3G/RX2/
DT2/KBI3
Legend:
Note 1:
PORTB
LATB
TRISB
INTCON
INTCON2
INTCON3
ODCON
ANCON1
Legend: Shaded cells are not used by PORTB.
Name
Pin Name
2:
3:
4:
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Pin assignment only available for 28-pin devices (PIC18F2XK80).
Default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set.
Default pin assignment for T0CKI when the T0CKMX Configuration bit is set.
Default pin assignment for T3CKI for 28, 40 and 44-pin devices. Alternate pin assignment for T3CKI for 64-pin devices
when T3CKMX is cleared.
GIE/GIEH
TRISB7
SSPOD
INT2IP
LATB7
RBPU
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
RB7
PORTB FUNCTIONS (CONTINUED)
—
Function
T0CKI
T3CKI
CK2
RX2
TX2
DT2
CCP5
KBI1
PGC
KBI2
PGD
KBI3
RB5
RB6
RB7
T3G
(1)
(1)
(1)
(1)
(3)
(4)
PEIE/GIEL
INTEDG0
ANSEL14
CCP5OD
TRISB6
INT1IP
LATB6
Bit 6
RB6
Setting
TRIS
0
1
x
x
0
1
1
0
1
x
0
0
1
1
0
1
x
x
x
1
1
1
1
ANSEL13
INTEDG1
CCP4OD
TMR0IE
TRISB5
INT3IE
LATB5
I/O
Bit 5
RB5
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O Type
Preliminary
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ANSEL12
INTEDG2
CCP3OD
TRISB4
INT0IE
INT2IE
LATB4
Bit 4
RB4
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Timer0 clock input.
Timer3 clock input.
CCP5 compare/PWM output. Takes priority over port data.
CCP5 capture input.
Interrupt-on-pin change.
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Serial execution (ICSP™) clock input for ICSP and ICD operation.
Asynchronous serial data output (EUSART module); takes priority
over port data.
Synchronous serial clock output (EUSART module); user must
configure as an input.
Synchronous serial clock input (EUSART module); user must
configure as an input.
Interrupt-on-pin change.
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
Timer3 external clock gate input.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (AUSART module); takes priority
over port data.
Synchronous serial data input (AUSART module); user must
configure as an input.
Interrupt-on-pin change.
INTEDG3
ANSEL11
CCP2OD
TRISB3
INT1IE
LATB3
RBIE
Bit 3
RB3
ANSEL10
CCP1OD
TMR0IP
TRISB2
TMR0IF
LATB2
INT3IF
Description
Bit 2
RB2
2011 Microchip Technology Inc.
ANSEL9
TRISB1
INT0IF
INT3IP
INT2IF
LATB1
U2OD
Bit 1
RB1
ANSEL8
TRISB0
INT1IF
LATB0
U1OD
RBIF
RBIP
Bit 0
RB0
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