PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 527
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F46K80-I/P
Manufacturer Part Number
PIC18F46K80-I/P
Description
40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F46K80-I/P
A/d Inputs
11-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
1K Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F46K80-I/PT
Manufacturer:
BROADCOM
Quantity:
101
Company:
Part Number:
PIC18F46K80-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F46K80-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2011 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
If CNT
PC
If CNT
PC
Q1
Q1
Q1
register ‘f’
operation
operation
operation
Test f, Skip if 0
TSTFSZ f {,a}
0 f 255
a [0,1]
skip if f = 0
None
If ‘f’ = 0 , the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
=
=
=
=
by a 2-word instruction.
Address (HERE)
00h,
Address (ZERO)
00h,
Address (NZERO)
TSTFSZ
:
:
011a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
CNT, 1
ffff
for details.
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
Preliminary
PIC18F66K80 FAMILY
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
literal ‘k’
Exclusive OR Literal with W
XORLW k
0 k 255
(W) .XOR. k W
N, Z
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
1
1
XORLW
Read
Q2
0000
B5h
1Ah
0AFh
1010
Process
Data
Q3
DS39977C-page 527
kkkk
Write to
Q4
W
kkkk
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