PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 418
PIC18F46K80-I/P
Manufacturer Part Number
PIC18F46K80-I/P
Description
40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F46K80-I/P
A/d Inputs
11-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
1K Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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PIC18F66K80 FAMILY
REGISTER 27-23: BnCON: TX/RX BUFFER ‘n’ CONTROL REGISTERS IN TRANSMIT MODE
DS39977C-page 418
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
TXBIF
R/W-0
2:
3:
4:
5:
(3)
These registers are available in Mode 1 and 2 only.
Clearing this bit in software while the bit is set will request a message abort.
This bit is automatically cleared when TXREQ is set.
While TXREQ is set or a transmission is in progress, Transmit Buffer registers remain read-only.
These bits set the order in which the Transmit Buffer register will be transferred. They do not alter the CAN
message identifier.
TXBIF: Transmit Buffer Interrupt Flag bit
1 = A message was successfully transmitted
0 = No message was transmitted
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits
0 = Automatically cleared when the message is successfully sent
RTREN: Automatic Remote Transmission Request Enable bit
1 = When a remote transmission request is received, TXREQ will be automatically set
0 = When a remote transmission request is received, TXREQ will be unaffected
TXPRI<1:0>: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
TXABT
R-0
[0 n 5, TXnEN (BSEL0<n>) = 1]
(3)
W = Writable bit
‘1’ = Bit is set
TXLARB
R-0
(3)
TXERR
R-0
Preliminary
(5)
(2,4)
(3)
(3)
(3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXREQ
R/W-0
(1)
(3)
(3)
(2,4)
RTREN
R/W-0
2011 Microchip Technology Inc.
x = Bit is unknown
TXPRI1
R/W-0
(5)
TXPRI0
R/W-0
bit 0
(5)
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