PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 274
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PIC18F46K80-I/P
Manufacturer Part Number
PIC18F46K80-I/P
Description
40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F46K80-I/P
A/d Inputs
11-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
1K Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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PIC18F66K80 FAMILY
20.1
The Enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
The CCP1CON register is modified to allow control
over four PWM outputs: ECCP1/P1A, P1B, P1C and
P1D. Applications can use one, two or four of these
outputs.
The outputs that are active depend on the ECCP
operating mode selected. The pin assignments are
summarized in
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the P1M<1:0>
and CCP1M<3:0> bits. The appropriate TRIS direction
bits for the port pins must also be set as outputs.
20.1.1
The ECCP modules use Timers, 1, 2, 3 and 4, depend-
ing on the mode selected. These timers are available to
CCP modules in Capture, Compare or PWM modes, as
shown in
TABLE 20-1:
The assignment of a particular timer to a module is
determined by the Timer to ECCP enable bits in the
CCPTMRS register
between the two modules are depicted in
Capture operations are designed to be used when the
timer is configured for Synchronous Counter mode.
Capture operations may not work as expected if the
associated timer is configured for Asynchronous Counter
mode.
DS39977C-page 274
Capture
Compare
PWM
ECCP Mode
ECCP Outputs and Configuration
Table
ECCP MODULE AND TIMER
RESOURCES
Table
20-1.
ECCP MODE – TIMER
RESOURCE
(Register
20-2.
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
Timer Resource
20-2). The interactions
Figure
20-1.
Preliminary
20.2
In Capture mode, the CCPR1H:CCPR1L register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
ECCP1 pin. An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every fourth rising edge
• Every 16
The event is selected by the mode select bits,
CCP1M<3:0> (CCP1CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP1IF, is set
(PIR3<1>). The flag must be cleared by software. If
another capture occurs before the value in the
CCPR1H/L register is read, the old captured value is
overwritten by the new captured value.
20.2.1
In Capture mode, the appropriate ECCP1 pin should be
configured as an input by setting the corresponding
TRIS direction bit.
Note:
Capture Mode
th
ECCP PIN CONFIGURATION
If the ECCP1 pin is configured as an out-
put, a write to the port can cause a capture
condition.
rising edge
2011 Microchip Technology Inc.
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