ICS1893AF IDT, Integrated Device Technology Inc, ICS1893AF Datasheet - Page 79

• Manufacturer Part Number: ICS1893AF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893AF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893AF

8.8.2 Parallel Detection Fault (bit 6.4)
8.8.3 Link Partner Next Page Able (bit 6.3)
8.8.4 Next Page Able (bit 6.2)
8.8.5 Page Received (bit 6.1)
8.8.6 Link Partner Auto-Negotiation Able (bit 6.0)
ICS1893AF, Rev. D 10/26/04
The ICS1893AF sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection
fault occurs when the ICS1893AF cannot disseminate the technology being used by its remote link partner.
Bit 6.4 is a latching high (LH) status bit. (For more information on latching high and latching low bits, see
Section 8.1.4.1, “Latching High Bits”
Bit 6.3 is a status bit that reports the capabilities of the remote link partner to support the Next Page
features of the auto-negotiation process. The ICS1893AF sets this bit to a logic one if the remote link
partner sets the Next Page bit in its Link Control Word.
Bit 6.2 is a status bit that reports the capabilities of the ICS1893AF to support the Next Page features of the
auto-negotiation process. The ICS1893AF sets this bit to a logic one to indicate that it can support these
features.
The ICS1893AF sets its Page Received bit to a logic one whenever a new Link Control Word is received
and stored in its Auto-Negotiation link partner ability register. The Page Received bit is cleared to logic zero
on a read of the Auto-Negotiation Expansion Register.
Bit 6.1 is a latching high (LH) status bit. (For more information on latching high and latching low bits, see
Section 8.1.4.1, “Latching High Bits”
If the ICS1893AF:
•
•
Does not receive Fast Link Pulse bursts from its remote link partner, then this bit remains a logic zero.
Receives valid FLP bursts from its remote link partner (thereby indicating that it can participate in the
auto-negotiation process), then the ICS1893AF sets this bit to a logic one.
ICS1893AF Data Sheet - Release
Copyright © 2004, Integrated Circuit Systems, Inc.
and
and
Section 8.1.4.2, “Latching Low
Section 8.1.4.2, “Latching Low
All rights reserved.
79
Chapter 8 Management Register Set
Bits”.)
Bits”.)
October, 2004