ICS1893AF IDT, Integrated Device Technology Inc, ICS1893AF Datasheet - Page 87

• Manufacturer Part Number: ICS1893AF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893AF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893AF

8.12 Register 17: Quick Poll Detailed Status Register
ICS1893AF, Rev. D 10/26/04
Table 8-18
register used to provide an STA with detailed status of the ICS1893AF operations. During reset, it is
initialized to pre-defined default values.
Note:
1. For an explanation of acronyms used in
2. Most of this register’s bits are latching high or latching low, which allows the ICS1893AF to capture and
3. Although some of these status bits are redundant with other management registers, the ICS1893AF
Table 8-18. Quick Poll Detailed Status Register (register 17 [0x11])
17.15 Data rate
17.14 Duplex
17.13 Auto-Negotiation
17.12 Auto-Negotiation
17.11
17.10 100Base-TX signal
17.9
17.8
17.7
17.6
17.5
17.4
17.3
17.2
17.1
17.0
Bit
ICS1893AF Data Sheet - Release
save the occurrence of an event for an STA to read. (For more information on latching high and latching
low bits, see
provides this group of bits to minimize the number of Serial Management Cycles required to collect the
status data.
Progress Monitor Bit 2
Progress Monitor Bit 1
Auto-Negotiation
Progress Monitor Bit 0
lost
100BasePLL Lock
Error
False Carrier detect
Invalid symbol
detected
Halt Symbol detected
Premature End
detected
Auto-Negotiation
complete
100Base-TX signal
detect
Jabber detect
Remote fault
Link Status
lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only
Definition
Section 8.1.4.1, “Latching High Bits”
Copyright © 2004, Integrated Circuit Systems, Inc.
10 Mbps
Half duplex
Reference Decode Table
Reference Decode Table
Reference Decode Table
Valid signal
PLL locked
Normal Carrier or Idle
Valid symbols observed
No Halt Symbol received
Normal data stream
Auto-Negotiation in
process
Signal present
No jabber detected
No remote fault detected
Link is not valid
When Bit = 0
All rights reserved.
Table
87
8-18, see
and
Full duplex
Signal lost
PLL failed to lock
False Carrier
Invalid symbol received
Halt Symbol received
Stream contained two
IDLE symbols
Auto-Negotiation
complete
No signal present
Jabber detected
Remote fault detected
100 Mbps
Reference Decode Table
Reference Decode Table
Reference Decode Table
Link is valid
Section 8.1.4.2, “Latching Low
When Bit = 1
Chapter 1, “Abbreviations and
Chapter 8 Management Register Set
cess
Ac-
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
LMX
LMX
LMX
LH
LH
SF
LH
LH
LH
LH
LH
LH
LL
Bits”.)
–
–
–
–
Acronyms”.
October, 2004
fault
De-
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Hex
–
0
0
0