ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 91

• Manufacturer Part Number: ICS1893YI-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893YI-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 1893YI-10LF

7.11.7 Invalid Error Code Test (bit 16.2)
7.11.8 ICS Reserved (bit 16.1)
7.11.9 Stream Cipher Disable (bit 16.0)
ICS1893Y-10 Rev F 1/20/04
The Invalid Error Code Test bit allows an STA to force the ICS1893Y-10 to transmit symbols that are
typically classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding
and the serial transmit data stream by allowing generation of bit patterns that are considered invalid by the
ISO/IEC 4B/5B definition.
When this bit is logic:
•
•
Table 7-17. Invalid Error Code Translation Table
See
The Stream Cipher Disable bit allows an STA to control whether the ICS1893Y-10 employs the Stream
Cipher Scrambler in the transmit and receive data paths. When this bit is set to logic:
•
•
Note:
Symbol
Zero, the ISO/IEC defined 4B/5B translation takes place.
One – and the TXER signal is asserted by the MAC/repeater – the MII input nibbles are translated
according to
Zero, the Stream Cipher Encoder and Decoder are both enabled for normal operations.
One, the Stream Cipher Encoder and Decoder are disabled. This action results in an unscrambled data
stream (for example, the ICS1893Y-10 transmits unscrambled IDLES, and so forth.
V (S)
ICS1893Y-10 - Release
Section 7.11.2, “ICS Reserved (bits
V
V
V
V
H
V
V
R
V
V
K
V
T
J
I
The Stream Cipher Scrambler can be used only for 100-MHz operations.
Invalid Code
Invalid Code
Invalid Code
Invalid Code
Error
Invalid Code
Invalid Code
ESD
Invalid Code
ESD
Invalid Code
SSD
Invalid Code
Invalid Code
SSD
Idle
Table
Meaning
7-17.
MII Input
Copyright © 2004, Integrated Circuit Systems, Inc.
Nibble
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
16.14:11)”, the text for which also applies here.
Translation
00000
00001
00010
00101
00000
10000
00011
00100
00110
01101
01100
10001
11001
11000
00111
All rights reserved.
11111
91
Chapter 7 Management Register Set
January, 2004