WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 182
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WM8310GEB/V
Manufacturer Part Number
WM8310GEB/V
Description
POWER MANAGEMENT SUBSYSTEM, 169BGA
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8310GEBV.pdf
(284 pages)
Specifications of WM8310GEB/V
Supply Voltage
7V
No. Of Step-down Dc - Dc Converters
4
No. Of Ldo Regulators
11
Digital Ic Case Style
BGA
No. Of Pins
169
No. Of Regulated Outputs
13
Operating Temperature Range
-40°C To
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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WM8310
REGISTER
R16405
(4015h)
Interrupt
Status 5
Register 4015h Interrupt Status 5
REGISTER
R16407
(4017h) IRQ
Config
Register 4017h IRQ Config
w
ADDRESS
ADDRESS
BIT
BIT
11
10
9
8
7
6
5
4
3
2
1
0
1
0
GP12_EINT
GP11_EINT
GP10_EINT
GP9_EINT
GP8_EINT
GP7_EINT
GP6_EINT
GP5_EINT
GP4_EINT
GP3_EINT
GP2_EINT
GP1_EINT
LABEL
LABEL
IRQ_OD
IM_IRQ
DEFAULT
DEFAULT
0
0
0
0
0
0
0
0
0
0
0
0
1
0
GPIO12 interrupt.
(Trigger is controlled by GP12_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO11 interrupt.
(Trigger is controlled by GP11_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO10 interrupt.
(Trigger is controlled by GP10_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO9 interrupt.
(Trigger is controlled by GP9_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO8 interrupt.
(Trigger is controlled by GP8_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO7 interrupt.
(Trigger is controlled by GP7_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO6 interrupt.
(Trigger is controlled by GP6_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO5 interrupt.
(Trigger is controlled by GP5_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO4 interrupt.
(Trigger is controlled by GP4_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO3 interrupt.
(Trigger is controlled by GP3_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO2 interrupt.
(Trigger is controlled by GP2_INT_MODE)
Note: Cleared when a ‘1’ is written.
GPIO1 interrupt.
(Trigger is controlled by GP1_INT_MODE)
Note: Cleared when a ‘1’ is written.
IRQ pin configuration
0 = CMOS
1 = Open Drain
IRQ pin output mask
0 = Normal
1 = IRQ output is masked
DESCRIPTION
DESCRIPTION
PP, December 2009, Rev 3.0
REFER TO
REFER TO
Pre-Production
182
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