ispPAC-POWR6AT6-01N32I Lattice, ispPAC-POWR6AT6-01N32I Datasheet - Page 15

• Manufacturer Part Number: ispPAC-POWR6AT6-01N32I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
• Manufacturer: Lattice

Specifications of ispPAC-POWR6AT6-01N32I

• Number Of Voltages Monitored: 6
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3-10. Digital Closed Loop Trim Operation
The closed loop trim cycle interval is programmable and is set by the update rate control register. The following
table lists the programmable update interval that can be selected by the update rate register.
Table 3-2. Output DAC Update Rate in Digital Closed Loop Mode
Closed Loop Trim Control Using the CLTENb Pin
There is a one-to-one relationship between the selected TrimCell and the corresponding VMON input for the closed
loop operation. For example, if TrimCell 3 is used to control the power supply in the closed loop trim mode, VMON3
must be used to monitor its output power supply voltage.
The CLTENb enable pin (active low) simultaneously starts the closed loop trimming process for all ispPAC-
POWR6AT6 trim outputs so configured. Behavior of individual trim output pins is defined using Lattice PAC-
Designer design software and stored in the ispPAC-POWR6AT6's non-volatile E
closed-loop trim control option, two other configuration alternatives are available. The first stores a fixed, or static,
value for a given trim output in E
an external microcontroller via the ispPAC-POWR6AT6's I
the CLTENb pin, however.
When the ispPAC-POWR6AT6's CLTENb pin goes low, closed-loop trimming is enabled. When CLTENb subse-
quently goes high, there is a brief delay after which closed-loop trimming is suspended. The delay is the time
required for ispPAC-POWR6AT6 control logic to complete a trim update cycle. Table 3-2 shows typical times for
update cycles based on which of four trim rates is initially chosen in PAC-Designer. When the trim process is
halted, it should also be noted the trim output DACs have constant voltage output levels (corresponding to their last
input code setting). This condition can be safely maintained indefinitely, but resuming closed-loop trimming (by tak-
ing CLTENb low) better insures power supplies remain precisely adjusted under all possible conditions. When re-
enabled, closed-loop trimming restarts where it left off. In this sense, the CLTENb pin can be thought of as a
“pause” control for closed-loop trim.
POWR6AT6
Three-State
COMPARE
DIGITAL
(+1/0/-1)
SETPOINT
(E
2
CMOS)
CONTROL
E
UPDATE
2
RATE
CMOS
POLARITY
CHANNEL
(E
2
+/-1
CMOS)
2
CMOS memory. The second enables dynamic trim adjustments to be made using
E
DAC Register I
DAC Register 3
2
DAC Register 2
DAC Register 1
DAC Register 0
CMOS Registers
Trim Register
Closed Loop
Control Value
Update Rate
00
01
10
11
2
C
Control (E
3-15
Profile 0 Mode
2
C interface bus. Neither of these options is affected by
2
Profile Control
CMOS)
Interval
1.06 ms
8.74 ms
16.9 ms
Update
432 µs
ADC
TrimCell
DAC
ispPAC-POWR6AT6 Data Sheet
VMONx
TRIMx
2
CMOS memory. In addition to a
*Indicates resistor network (see Figure 8).
R*
TRIMIN
VOUT
GND
CONVERTER
DC-DC