ispPAC-POWR6AT6-01N32I Lattice, ispPAC-POWR6AT6-01N32I Datasheet - Page 31

• Manufacturer Part Number: ispPAC-POWR6AT6-01N32I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
• Manufacturer: Lattice

Specifications of ispPAC-POWR6AT6-01N32I

• Number Of Voltages Monitored: 6
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
RESET - This command resets the ispPAC-POWR6AT6 to a condition near that of the power-on reset state (refer to
2
reset command via JTAG or I
C section of this data sheet for more details and known exceptions).
ERASE_DONE_BIT - This instruction erases the ispPAC-POWR6A6 DONE bit.
CFG_VERIFY - This instruction is used to verify the contents of the selected configuration array column. This spe-
cific column is preselected by using CFG_ADDRESS instruction.
CFG_ERASE - This instruction will bulk erase the configuration array. The action occurs at the second rising edge
of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction).
CFG_ADDRESS - This instruction is used to set the address of the configuration array for subsequent program or
read operations.
CFG_DATA_SHIFT - This instruction is used to shift data into the configuration register prior to programming or
reading.
CFG_PROGRAM - This instruction programs the selected configuration array column. This specific column is pre-
selected by using CFG_ADDRESS instruction. The programming occurs at the second rising edge of the TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction).
PROGRAM_DONE_BIT - This instruction programs the ispPAC-POWR6A6 DONE bit.
2
Note: Before any of the above programming instructions are executed, the respective E
CMOS bits need to be
erased using the corresponding erase instruction
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