SAF1760BE/V1,557 NXP Semiconductors, SAF1760BE/V1,557 Datasheet - Page 53

• Manufacturer Part Number: SAF1760BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1760BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 57.
[1]
Table 58.
SAF1760_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 10
9
8
7
The reserved bits should always be written with the reset value.
Symbol
-
ISO_IRQ_E
ATL_IRQ_E
INT_IRQ_E
Interrupt Enable register (address 0314h) bit allocation
Interrupt Enable register (address 0314h) bit description
INT_IRQ_E CLKREADY
8.4.2 Interrupt Enable register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
This register allows enabling or disabling of the IRQ generation because of various events
as described in
Description
reserved; write logic 0
ISO IRQ Enable: Controls the IRQ assertion when one or more ISO PTDs matching the ISO
IRQ Mask AND or ISO IRQ Mask OR register bits combination are completed.
0 — No IRQ will be asserted when ISO PTDs are completed.
1 — IRQ will be asserted.
For details, see
ATL IRQ Enable: Controls the IRQ assertion when one or more ATL PTDs matching the ATL
IRQ Mask AND or ATL IRQ Mask OR register bits combination are completed.
0 — No IRQ will be asserted when ATL PTDs are completed.
1 — IRQ will be asserted.
For details, see
INT IRQ Enable: Controls the IRQ assertion when one or more INT PTDs matching the INT
IRQ Mask AND or INT IRQ Mask OR register bits combination are completed.
0 — No IRQ will be asserted when INT PTDs are completed.
1 — IRQ will be asserted.
For details, see
R/W
R/W
R/W
R/W
_E
30
22
14
0
0
0
6
0
HCSUSP_E
Table
Section
Section
Section
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 9 November 2009
57.
reserved
7.4.
7.4.
7.4.
reserved
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
[1]
DMAEOT
[1]
[1]
INT_E
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
reserved
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
[1]
ISO_IRQ_E
SOFITLINT
R/W
R/W
R/W
R/W
_E
25
17
0
0
9
0
1
0
SAF1760
© NXP B.V. 2009. All rights reserved.
reserved
ATL_IRQ
R/W
R/W
R/W
R/W
_E
53 of 110
24
16
0
0
8
0
0
0
[1]