MT48LC16M8A2P-75L Micron Technology Inc, MT48LC16M8A2P-75L Datasheet - Page 67
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MT48LC16M8A2P-75L
Manufacturer Part Number
MT48LC16M8A2P-75L
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC16M8A2P-75L.pdf
(74 pages)
Specifications of MT48LC16M8A2P-75L
Organization
16Mx8
Density
128Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Figure 51:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMU
COMMAND
A0–A9, A11
BA0, BA1
DQM /
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
Single WRITE – Without Auto Precharge
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <D
3. x16: A9 and A11 = “Don’t Care.”
NOP
x8: A11 = “Don’t Care.”
DISABLE AUTO PRECHARGE
t CMS
t CL
t DS
COLUMN m 3
WRITE
BANK
T2
D
IN
t CMH
t CH
t DH
m
t WR
4
NOP 2
T3
67
IN
m> and the PRECHARGE command, regardless of frequency.
NOP 2
T4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PRECHARGE
SINGLE BANK
ALL BANKS
T5
BANK
t RP
128Mb: x4, x8, x16 SDRAM
NOP
T6
©1999 Micron Technology, Inc. All rights reserved.
ACTIVE
BANK
ROW
T7
Timing Diagrams
NOP
T8
DON’T CARE