MT46V128M8P-6T IT:ATR Micron Technology Inc, MT46V128M8P-6T IT:ATR Datasheet - Page 48

• Manufacturer Part Number: MT46V128M8P-6T IT:ATR
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V128M8P-6T IT:ATR

• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 230mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

CAS Latency (CL)
Figure 22:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
CAS Latency
Note:
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 22. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 29 on page 49 indi-
cates the operating frequencies at which each CL setting can be used.
Command
Command
Command
BL = 4 in the cases shown; shown with nominal
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
READ
READ
READ
T0
T0
T0
CL = 2
CL = 2.5
CL = 3
NOP
NOP
NOP
T1
T1
T1
48
Transitioning Data
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
NOP
NOP
T2
T2
T2
t
T2n
T2n
AC,
1Gb: x4, x8, x16 DDR SDRAM
t
DQSCK, and
NOP
NOP
NOP
T3
T3
T3
Don’t Care
©2003 Micron Technology, Inc. All rights reserved.
T3n
T3n
T3n
t
DQSQ.
Operations