STM32F101RDT6TR STMicroelectronics, STM32F101RDT6TR Datasheet - Page 104

• Manufacturer Part Number: STM32F101RDT6TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F101RDT6TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 36MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 51
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision history
104/106
Table 65.
30-Mar-2009
Date
Document revision history (continued)
Revision
5
I/O information clarified
corrected in
STM32F101xE features and peripheral
In
– I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15
– PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
PG14 pin description modified in
Figure 6: Memory map on page 33
Note modified in
code with data processing running from Flash
current consumption in Sleep mode, code running from Flash or
Figure
changed).
Table 21: High-speed external user clock characteristics
Low-speed user external clock characteristics
ACC
FSMC configuration modified for
Notes modified below
SRAM/PSRAM/NOR read waveforms
non-multiplexed SRAM/PSRAM/NOR write
t
SRAM/PSRAM/NOR read timings
multiplexed NOR/PSRAM write
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings.
In
Table 38: Synchronous non-multiplexed PSRAM write
– t
– t
– t
Figure 25: Synchronous multiplexed NOR/PSRAM read
Figure 26: Synchronous multiplexed PSRAM write timings
Figure 28: Synchronous non-multiplexed PSRAM write timings
modified. Small text changes.
w(NADV)
updated
column to Remap column.
Table 5: High-density STM32F101xx pin
Table 36: Synchronous multiplexed PSRAM write timings
v(Data-CLK)
d(CLKL-Data)
h(CLKL-DV)
Doc ID 14610 Rev 7
HSI
14,
max values modified in
values modified in
Figure 15
Table 2: STM32F101xC, STM32F101xD and
/ t
renamed as t
min value removed and max value added
h(CLKL-ADV)
Table 14: Maximum current consumption in Run mode,
STM32F101xC, STM32F101xD, STM32F101xE
and
Figure 21: Asynchronous non-multiplexed
on page
Figure 16
removed
d(CLKL-Data)
Table 31: Asynchronous non-multiplexed
Changes
timings. t
Table 25: HSI oscillator characteristics
Asynchronous waveforms and
1. Number of ADC peripherals
Table 6: FSMC pin
and
modified.
show typical curves (titles
and
Table 34: Asynchronous
counts.
h(Data_NWE)
Figure 22: Asynchronous
definitions:
waveforms.
modified.
and
Table 16: Maximum
definition.
modified in
timings:
timings,
and
and
and
Table 22:
timings.
RAM.