STM32W108C8U63TR STMicroelectronics, STM32W108C8U63TR Datasheet - Page 139
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STM32W108C8U63TR
Manufacturer Part Number
STM32W108C8U63TR
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32W108C8U63TR.pdf
(207 pages)
Specifications of STM32W108C8U63TR
Applications
RF4CE, Remote Control
Core Processor
ARM® Cortex-M3™
Program Memory Type
FLASH (64 kB)
Controller Series
STM32W
Ram Size
8K x 8
Interface
I²C, SPI, UART/USART
Number Of I /o
24
Voltage - Supply
1.18 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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STM32W108C8
10.3.2
31
15
30
14
Timer x control register 2 (TIMx_CR2)
Address offset: 0xE004 (TIM1) and 0xF004 (TIM2)
Reset value:
Bit 1 TIM_UDIS: Update Disable
Bit 0 TIM_CEN: Counter Enable
Bit 7 TIM_TI1S: TI1 Selection
29
13
0: An update event is generated as soon as a counter overflow occurs, a software update is
generated, or a hardware reset is generated by the slave mode controller. Shadow registers are
then loaded with their buffer register values.
1: An update event is not generated and shadow registers keep their value (TIMx_ARR,
TIMx_PSC, TIMx_CCRy). The counter and the prescaler are reinitialized if the TIM_UG bit is
set or if a hardware reset is received from the slave mode controller.
0: Counter disabled.
1: Counter enabled.
Note: External clock, gated mode and encoder mode can work only if the TIM_CEN bit has
0: TI1M (input of the digital filter) is connected to TI1 input.
1: TI1M is connected to the TI_HALL inputs (XOR combination).
28
12
Reserved
been previously set by software. Trigger mode sets the TIM_CEN bit automatically
through hardware.
27
11
0x0000 0000
26
10
25
9
Doc ID 018587 Rev 1
24
8
Reserved
TIM_TI
1S
23
rw
7
22
6
TIM_MMS
rw
21
5
20
4
General-purpose timers
19
3
18
2
Reserved
17
1
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