STM32W108CBU61TR STMicroelectronics, STM32W108CBU61TR Datasheet - Page 155

• Manufacturer Part Number: STM32W108CBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU61TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
10.3.17
10.3.18
31
15
31
15
Reserved
30
14
30
14
Bits [1:0] TIM1_EXTRIGSEL
Timer x interrupt configuration register (INT_TIMxCFG)
Address offset: 0xA840 (TIM1) and 0xA844 (TIM2)
Reset value:
Timer x interrupt flag register (INT_TIMxFLAG)
Address offset: 0xA800 (TIM1) and 0xA804 (TIM2)
Reset value:
Bit 3 TIM_ORRSVD
Bit 2 TIM_CLKMSKEN
Bit 6 INT_TIMTIF: Trigger interrupt enable.
Bit 4 INT_TIMCC4IF: Capture or compare 4 interrupt enable.
Bit 3 INT_TIMCC3IF: Capture or compare 3 interrupt enable.
Bit 2 INT_TIMCC2IF: Capture or compare 2 interrupt enable.
Bit 1 INT_TIMCC1IF: Capture or compare 1 interrupt enable.
Bit 0 INT_TIMUIF: Update interrupt enable.
29
13
29
13
Reserved: this bit must always be set to 0.
Enables TIM2MSK when TIM2CLK is selected as the external trigger: 0 = TIM2MSK not used,
1 = TIM2CLK is ANDed with the TIM2MSK input.
Selects the external trigger used in external clock mode 2: 0 = PCLK, 1 = calibrated 1 kHz
clock, 2 = 32 kHz reference clock (if available), 3 = TIM2CLK pin.
28
12
28
12
Reserved
INT_TIMRSVD
27
11
27
11
0x0000 0000
0x0000 0000
r
26
10
26
10
25
25
9
9
Doc ID 16252 Rev 8
24
24
8
8
Reserved
Reserved
Reserved
23
23
7
7
INT_TI
INT_TI
MTIF
MTIF
22
22
rw
rw
6
6
Reserv
Reserv
21
ed
21
ed
5
5
INT_T
INT_T
IMCC
IMCC
4IF
4IF
20
rw
20
rw
4
4
General-purpose timers
MCC3I
MCC3I
INT_TI
INT_TI
19
rw
19
rw
3
F
3
F
MCC2I
MCC2I
INT_TI
INT_TI
18
18
rw
rw
2
F
2
F
MCC1I
MCC1I
INT_TI
INT_TI
17
17
rw
rw
1
F
1
F
155/209
INT_TI
INT_TI
MUIF
MUIF
16
rw
16
rw
0
0