5V49EE703NDGI8 IDT, Integrated Device Technology Inc, 5V49EE703NDGI8 Datasheet - Page 23

• Manufacturer Part Number: 5V49EE703NDGI8
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Programmable PLL Clock Synthesizerr

Specifications of 5V49EE703NDGI8

• Number Of Elements: 4
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN EP
• Output Frequency Range: 0.001 to 200MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / Rohs Status: Compliant

IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Addr
0x5C
0x5D
0x6C
0x6D
0x7C
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
IDT5V49EE703
EEPROM PROGRAMMABLE CLOCK GENERATOR
Register
Default
Value
Hex
0C
0C
0C
0C
0C
0C
00
00
00
00
00
00
03
03
03
03
03
03
00
00
00
00
00
00
00
00
00
00
00
00
01
03
00
00
00
00
00
00
00
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7
OEM0[1:0]
OEM1[1:0]
OEM3[1:0]
OEM5[1:0]
6
IP3[3:0]_CFG4
IP3[3:0]_CFG5
IP3[3:0]_CFG0
IP3[3:0]_CFG1
IP3[3:0]_CFG2
IP3[3:0]_CFG3
5
SLEW0[1:0]
SLEW1[1:0]
SLEW2[1:0]
SLEW3[1:0]
SLEW5[1:0]
SLEW6[1:0]
4
SSVCO[7:0]_CFG0
SSVCO[7:0]_CFG1
SSVCO[7:0]_CFG2
SSVCO[7:0]_CFG3
SSVCO[7:0]_CFG4
SSVCO[7:0]_CFG5
SS_D3[7:0]_CFG4
SS_D3[7:0]_CFG5
SS_D3[7:0]_CFG0
SS_D3[7:0]_CFG1
SS_D3[7:0]_CFG2
SS_D3[7:0]_CFG3
N3[7:0]_CFG4
N3[7:0]_CFG5
N3[7:0]_CFG0
N3[7:0]_CFG1
N3[7:0]_CFG2
N3[7:0]_CFG3
Reserved
Reserved
Reserved
Bit #
D3[6:0]_CFG0
D3[6:0]_CFG1
D3[6:0]_CFG2
D3[6:0]_CFG3
D3[6:0]_CFG4
D3[6:0]_CFG5
INV0
23
3
INV1[1:0]
INV3[1:0]
INV5[1:0]
Reserved
2
RZ3[3:0]_CFG4
RZ3[3:0]_CFG5
RZ3[3:0]_CFG0
RZ3[3:0]_CFG1
RZ3[3:0]_CFG2
RZ3[3:0]_CFG3
S1
1
Reserved
Reserved
Reserved
Reserved
Reserved
S3
0
IDT5V49EE703
CLOCK SYNTHESIZER
PLL3 Loop Parameter
PLL3 Reference Divide and input
sel
D3[6:0] - 127 step Ref Div
D3 = 0 means power down.
N - Feedback Divider
12 - 4095 (values of “0” through
“11” are not allowed)
SSVCO[7:0] - PLL3 Spread
Spectrum Loop Feedback
Counter
See Addr 0x80:0x85 for
SSVCO[15:8]
SS_D[7:0] - PLL3 Spread
Spectrum Reference Divide
Reserved
Output Controls
S1=1 - OUT1/OUT2 are from
DIV1/DIV2 respectively
S1=0 - Both from DIV2
S3 =1 - OUT3/OUT6 are from
DIV3/DIV6
S3=0 - Both from DIV6
OEM#–output enable mode
x0 - tristated
01 - park low
11 - park high
OEM0 controls OUT0 only
Output Controls
INV1 [CLK1, CLK2]
[0] - normal
[1] - invert clock
OEM1 controls OUT1/OUT2
OEM3 controls OUT3 and OUT6
together
OEM5 controls OUT5 and OUT5b
Description
REV F 022310