RC48F4400P0TB0EA Micron Technology Inc, RC48F4400P0TB0EA Datasheet - Page 31
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
RC48F4400P0TB0EA
Manufacturer Part Number
RC48F4400P0TB0EA
Description
Manufacturer
Micron Technology Inc
Datasheet
1.RC48F4400P0TB0EA.pdf
(88 pages)
Specifications of RC48F4400P0TB0EA
Cell Type
NOR
Density
512Mb
Interface Type
Parallel/Serial
Boot Type
Bottom
Address Bus
25b
Operating Supply Voltage (typ)
2.5/3/3.3V
Operating Temp Range
-40C to 85C
Package Type
EZBGA
Sync/async
Async/Sync
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
3.6V
Word Size
16b
Number Of Words
32M
Supply Current
31mA
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant
P33-65nm
10.1.4
Figure 8:
Note:
10.1.5
Note:
Datasheet
31
LK: Lock Setup Command, 60h; LK/D0h: Unlock Command; LK/01h: Lock Command; LK/2Fh: Lock-Down Command.
Block Locking State Diagram
Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see
Section 7.3, “Read Device Identifier” on page
addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the
addressed block’s lock-down bit.
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change
block locking during an erase operation, first issue the Erase Suspend command.
Monitor the Status Register until SR.7 and SR.6 are set, indicating the device is
suspended and ready to accept another command.
Next, write the desired lock command sequence to a block, which changes the lock
state of that block. After completing block lock or unlock operations, resume the erase
operation using the Erase Resume command.
A Lock Block Setup command followed by any command other than Lock Block, Unlock
Block, or Lock-Down Block produces a command sequence error and set Status
Register bits SR.4 and SR.5. If a command sequence error occurs during an erase
suspend, SR.4 and SR.5 remains set, even after the erase operation is resumed. Unless
the Status Register is cleared using the Clear Status Register command before
resuming the erase operation, possible erase errors may be masked by the command
sequence error.
W P # = V
W P # = V
IL
I H
= 0
= 1
P G M /E R A S E
A L L O W E D
[ 0 0 0 ]
[ 1 1 0 ]
[ 1 0 0 ]
V i r t u a l l o c k -
D 0 h
D 0 h
L K /
L K /
D 0 h
d o w n
L K /
0 1 h o r 2 F h
2 F h
L K /
L K /
0 1 h
L K /
0 1 h
L K /
[ 0 1 0 ]
c o m m a n d s
22). Data bits DQ[1:0] display the
A n y L o c k
P R E V E N T E D
P G M /E R A S E
2 F h
L K /
[ 0 0 1 ]
[ 0 1 1 ]
[ 1 1 1 ]
[ 1 0 1 ]
W P # t o g g l e
2 F h
L K /
i s d i s a b l e d b y
L o c k e d - d o w n
L o c k e d - d o w n
W P # = V
R e s e t D e f a u l t
R e s e t D e f a u l t
P o w e r - U p /
Order Number:320003-09
P o w e r - U p /
I H
Mar 2010