RC48F4400P0TB0EA Micron Technology Inc, RC48F4400P0TB0EA Datasheet - Page 33

• Manufacturer Part Number: RC48F4400P0TB0EA
• Manufacturer: Micron Technology Inc

Specifications of RC48F4400P0TB0EA

• Cell Type: NOR
• Density: 512Mb
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 25b
• Operating Supply Voltage (typ): 2.5/3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

P33-65nm
11.0
Table 10: Status Register Description
Notes:
1.
2.
Datasheet
33
Status Register (SR)
Device Write
Status
DWS
Bit
7
7
6
5
4
3
2
1
0
Always clear the Status Register prior to resuming erase operations. It avoids Status Register ambiguity when issuing
commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register
contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible
errors during the erase operation cannot be detected via the Status Register because it contains the previous error status
BEFP mode is only valid in main array.
Device Write Status (DWS)
Erase Suspend Status (ESS)
Erase Status
(ES)
Program
Status (PS)
VPP Status (VPPS)
Program Suspend Status
(PSS)
Block-Locked Status (BLS)
BEFP Write Status (BWS)
Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. SRD is automatically made available
following a Word Program, Block Erase, or Block Lock command sequence. Reads from
the device after any of these command sequences outputs the device’s status until
another valid command is written (e.g. the Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. SRD is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, when reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update SRD.
The Device Write Status bit (SR.7) provides overall status of the device. SR[6:1]
present status and error information about the program, erase, suspend, VPP, and
block-locked operations.
Suspend
Status
Erase
ESS
6
Name
Erase Status
Command
Sequence
Error
ES
5
0 = Device is busy; program or erase cycle in progress; SR.0 valid.
1 = Device is ready; SR[6:1] are valid.
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
SR.5
0 = VPP within acceptable limits during program or erase operation.
1 = VPP < V
0 = Program suspend not in effect.
1 = Program suspend in effect.
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
1 = BEFP in-progress.
0
0
1
1
Program
Status
PS
4
SR.4
0
1
0
1
PPLK
Description
Program or Erase operation successful.
Program error - operation aborted.
Erase error - operation aborted.
Command sequence error - command aborted.
during program or erase operation.
VPP Status
VPPS
3
Description
Program
Suspend
Status
PSS
2
Block-Locked
Status
BLS
Order Number:320003-09
1
Default Value = 0x80
Status
Write
BEFP
BWS
Mar 2010
0