M95256-WMN3TP/AB STMicroelectronics, M95256-WMN3TP/AB Datasheet - Page 17

• Manufacturer Part Number: M95256-WMN3TP/AB
• Manufacturer: STMicroelectronics

M95256-DR, M95256, M95256-W, M95256-R
5.4
Figure 8.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, the data byte on Serial Data Input (D) and the Chip Select
(S) driven High. Chip Select (S) must be driven High after the rising edge of Serial Clock (C)
that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock
(C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed.
The instruction sequence is shown in
Driving the Select (S) High at a byte boundary of the input data triggers the self timed Write
cycle, and continues for a period t
Table
be read to check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-
timed Write cycle t
Latch) is also reset when the Write cycle t
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 bits and the SRWD bit:
●
●
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b4, b1, b0 of the
Status Register. Bits b6, b5, b4 are always read as 0.
S
C
D
Q
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read only, as defined in
The SRWD bit (Status Register Write Disable bit), in accordance with the signal read
on the Write Protect pin (W), allows the user to set or reset the Write protection mode
of the Status Register itself, as defined in
Write Status Register (WRSR) instruction is not executed.
20). While the Write Status Register cycle is in progress, the Status Register may still
Read Status Register (RDSR) sequence
0
High Impedance
1
W
2
Instruction
, and is 0 when the Write cycle is completed. The WEL bit (Write Enable
3
4
5
Table
Doc ID 12276 Rev 17
6
W
7
W
2.
MSB
Write cycle.
7
(as specified in
8
Figure
6
Status Register Out
9 10 11 12 13 14 15
5
W
is completed.
4
9.
Table
3
2
Table
6. When in Write Protected mode, the
1
0
17,
MSB
7
6
Table
Status Register Out
5
4
18,
3
Table 19
2
1
Instructions
0
and
7
AI02031E
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