M95256-WMN3TP/AB STMicroelectronics, M95256-WMN3TP/AB Datasheet - Page 26

• Manufacturer Part Number: M95256-WMN3TP/AB
• Manufacturer: STMicroelectronics

Delivery state
6
7
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Delivery state
The device is delivered with all the memory array cells set to 1 (FFh). The Status Register
Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted into the device, the most
significant bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial
Clock (C) after Chip Select (S) goes low.
All output data bytes are shifted out of the device, the most significant bit first. The Serial
Data output (Q) is latched on the first falling edge of the Serial Clock (C) after the
instructions (such as the Read from Memory Array and Read Status Register instructions)
have been clocked into the device.
Figure 17
bus. Only one memory device is selected at a time, so only one memory device drives the
Serial Data output (Q) line at a time; the other memory devices are high impedance.
Figure 17. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
A pull-up resistor connected on each /S input (represented in
slave device on the SPI bus is not selected if the bus master leaves the /S line in the high
impedance state.
CS3
SPI Interface with
(ST6, ST7, ST9,
(CPOL, CPHA) =
ST10, Others)
(0, 0) or (1, 1)
Bus Master
CS2 CS1
shows an example of three memory devices connected to an MCU, on an SPI
SDO
SDI
SCK
R
R
Doc ID 12276 Rev 17
C Q D
S
SPI Memory
Device
W
V
CC
HOLD
V
M95256-DR, M95256, M95256-W, M95256-R
SS
R
C Q D
S
SPI Memory
Device
W
V
Figure
CC
HOLD
V
SS
R
7) ensures that each
C Q D
S
SPI Memory
Device
W
V
CC
HOLD
AI12304b
V
V
V
SS
CC
SS