Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 225
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
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Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
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Quantity:
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Table 108. I
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
7
6:5
4
3
2:1
Description
DMAIF – DMA interface mode.
0 = Used when software polling or interrupts are used to move data.
1 = Used when the DMA is used to move data. The TDRE and RDRF bits in the status register
are not affected but the I
rupt reflects only the error conditions. The assertion of TDRE causes a transmit DMA request.
The assertion of RDRF causes a receive DMA request.
MODE – Selects the I
00 = Master/Slave capable (supports multi-Master arbitration) with 7-bit slave address.
01 = Master/Slave capable (supports multi-Master arbitration) with 10-bit slave address.
10 = Slave Only capable with 7-bit address.
11 = Slave Only capable with 10-bit address.
IRM – Interactive receive mode
Valid in Slave mode when software needs to interpret each received byte before acknowledg-
ing. This bit is useful for processing the data bytes following a General Call Address or if soft-
ware wants to disable hardware address recognition.
0 = Acknowledge occurs automatically and is determined by the value of the NAK bit of the
I2CCTL register.
1 = A receive interrupt is generated for each byte received (address or data). The SCL is held
Low during the acknowledge cycle until software writes to the I2CCTL register. The value writ-
ten to the NAK bit of the I2CCTL register is output on SDA. This value allows software to
Acknowledge or Not Acknowledge after interpreting the associated address/data byte.
GCE – General call address enable
Enables reception of messages beginning with the General Call Address or START byte.
0 = Do not accept a message with the General Call Address or START byte.
1 = Do accept a message with the General Call Address or START byte. When an address
match occurs, the GCA and RD bits in the I
matched the General Call Address/START byte or not. Following the General Call Address
byte, software sets the IRM bit that allows software to examine the following data byte(s)
before acknowledging.
SLA[9:8] – Slave address bits 9 and 8
Initialize with the appropriate slave address value when using 10-bit Slave addressing. These
bits are ignored when using 7-bit Slave addressing.
2
C Mode Register (I2CMODE)
DMAIF
R/W
7
0
6
MODE[1:0]
R/W
2
0
C Controller operational mode
2
C interrupt is not asserted when TDRE or RDRF are set. The I
5
P R E L I M I N A R Y
IRM
R/W
4
0
FF_E246H
2
C Status Register indicates whether the address
GCE
R/W
Z16FMC Series Motor Control MCUs
3
0
2
SLA[9:8]
I2C Master/Slave Controller
R/W
Product Specification
0
1
2
DIAG
R/W
C inter-
0
0
203
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