Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 251
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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- Download datasheet (21Mb)
PS028702-1210
Linked List Setup and Operation
The software initially needs to create the descriptor lists and allocate the buffers for each
list. In addition, software needs to do the following:
1. Write the DMAxREQSEL to select the appropriate request source.
2. Set the CONTROL field in the descriptor (not the DMA) for the appropriate
3. Write the destination address to the destination field.
4. Write the source address to the source field.
5. Write the transfer length for this buffer.
6. If this descriptor has its
7. If there are additional descriptors in the list then set them up using the same procedure
After the descriptor has been set up, the software must write the DMAxLAR in the appro-
priate DMA with the address of the descriptor. The DMA performs the following:
1. Generate a request to the CPU.
2. Place the DMAxLAR address on the bus and fetch the CONTROL word from the
3. Fetch the Destination address from the descriptor and place it in the DMAxDAR
4. Fetch the Source address from the descriptor and place it in the DMAxSAR register in
operation:
–
–
–
–
–
–
–
–
–
–
descriptor.
listed above.
descriptor. This word is then placed in the DMAxCTL register of the DMA channel.
register in the DMA channel.
the DMA channel.
DMAxEN; set to 1
LOOP; set to 1 to not have the descriptor modified
TXSIZE; set the appropriate size for byte, word or quad
DSTCTL; set this for increment, decrement, or fixed
SRCCTL; set this for increment, decrement, or fixed
IEOB; set to 1 if an interrupt must be generated when this descriptor is closed
TXFR; set this bit if the LAR is used to point to the next descriptor
EOF, if it is an End Of Frame buffer then set this bit
HALT, if the DMA must stop at the end of this buffer then set this bit to one
CMDSTAT; set this field with a command for the selected peripheral
P R E L I M I N A R Y
TXFR
bit set then the LAR address to point to the next
Z16FMC Series Motor Control MCUs
Product Specification
DMA Controller
229
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