Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 246
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
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Z16FMC28AG20SG
Manufacturer:
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PS028702-1210
DMA Peripheral Interface signals
Buffer Closure
DMAxTXLN[15:8] is zero and DMAxTXLN[7:0] == DMAxLAR[23:16] then an inter-
rupt is generated. This function allows the DMA channel to generate an interrupt prior to
the buffer becoming empty.
The DMA uses two input signals, four output signals and two 4-bit buses to communicate
with the peripherals. The input signals are Request (REQ) and Request EOF. The output
signals are Acknowledge (ACK), Command Valid (CMDVLD), End Of Frame (EOF-
SYNC) and Read Status (RDSTAT). The two 4-bit busses are Command Bus (CMDBUS)
and Stat Bus (STATBUS).
A DMA transfer is initiated with the Request (REQ). When the DMA is servicing a
Request from a peripheral it will assert its acknowledge signal (ACK) to let the peripheral
know that a transfer is in progress. When the first byte of the transfer is written the CMD-
VLD is asserted and the command bits are placed on the CMDBUS. The peripheral needs
to latch the command from the bus when it sees this combination of signals.
If the
EOFSYNC signal is asserted on the final data transfer to the peripheral to signal that it is
the final byte in the frame.
After receiving the EOFSYNC signal the peripheral need to assert the Request EOF signal
to the DMA to let the DMA know that the descriptor is closed. This could be immediately
or at some later time if the data transferred still needs to be processed. For peripherals,
which do not support a Request EOF, the EOFSYNC is tied to Request EOF to terminate
the transfer.
After the Request EOF is asserted the DMA closes the descriptor. The DMA asserts the
ACK and RDSTAT signal, if the descriptor EOF bit is set. The peripheral, if it has status,
places it on the STATBUS. This status is then placed in the descriptor and DMA status bits
when it is closed.
If a peripheral needs to close a descriptor because of an error or the end of a packet is
reached then it asserts it is Request EOF. If the transfer length is not zero, then the DMA
will set the EOF bit, close the descriptor and generate an interrupt.
A DMA buffer closure is requested in two ways. The first is when the transfer length
reaches zero. The second is when the DMA receives a request End Of Frame from the
peripheral. When either of these cases occur, the DMA begins closure of the buffer.
Loop Mode Closure
If the LOOP bit is set then the current buffer descriptor is not modified. The DMAxLAR
increments or a new LAR value is fetched from the descriptor.
EOF
bit is set on the current buffer, and when the TXLN decrements to zero, the
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Product Specification
DMA Controller
224
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