Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 257
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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DMA Control Registers
Table 124. DMA Control Register A (DMAxCTL)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
Field
RESET
R/W
ADDR
Bits
15
14
13:12
11:10
DMA Control Register
Description
DMAxEN – DMA X enable.
If this bit is written directly then normal mode is executed. If this bit is read in from a descriptor
then linked list mode is executed.
0 = DMA is disabled.
1 = DMA is enabled.
LOOP – LOOP mode
0 = Descriptor is modified when the buffer is closed.
1 = Descriptor is not modified when buffer is closed.
TXSIZE – Transfer size
00 = Byte
01 = Word
10 = Quad
11 = Reserved
DSTCTL – Destination control register
00 = Destination address does not change
01 = Destination address increments
10 = Destination address decrements
11 = Reserved
DMAxEN
IEOB
R/W
R/W
15
0
7
0
This section describes the DMA control registers.
The DMA Control Register enables and controls DMA transfers (see Table 124).
LOOP
TXFR
R/W
R/W
14
0
6
0
FFE410H, FFE420H, FFE430H, FFE440H
FFE411H, FFE421H, FFE431H, FFE441H
EOF
R/W
R/W
13
0
5
0
TXSIZE
P R E L I M I N A R Y
HALT
R/W
R/W
12
0
4
0
R/W
R/W
11
Z16FMC Series Motor Control MCUs
0
3
0
DSTCTL
R/W
R/W
10
0
2
0
CMDSTAT
Product Specification
R/W
R/W
9
0
1
0
SRCCTL
DMA Controller
R/W
R/W
8
0
0
0
235
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