Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 297
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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Table 157. Status Register (DBGSTAT)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
7
6
5
4
3
Status Register
Description
RDRF – Receive data register full
This bit reflects the status of the Receive Data Register. When data is written to the Receive
Data Register, or data is transferred from the shift register to the Receive Data Register, this bit
is set to 1. When the Receive Data Register is read, this bit is cleared to zero. This bit is also
cleared to zero by writing a one to this bit.
0 = Receive Data Register is empty.
1 = Receive Data Register is full.
RXOV – Receive overrun
This bit is set when a Receive Overrun occurs. A Receive Overrun occurs when there is data in
the Receive Data Register and another byte is written to this register.
0 = Receive Overrun has not occurred
1 = Receive Overrun has occurred.
RXFE – Receive Framing error
This bit is set when a Receive Framing error has been detected. This bit is cleared by writing a
one to this bit.
0 = No Framing Error detected.
1 = Receive Framing Error detected.
RXBRK – Receive Break detect
This bit is set when a Break condition has been detected. This occurs when 10 or more bits
received are Low. This bit is cleared by writing a one to this bit.
0 = No Break detected.
1 = Break detected.
TDRE – Transmit Data Register empty
This bit reflects the status of the Transmit Data Register. When the Transmit Data Register is
written, this bit is cleared to zero. When data from the transmit data register is read or trans-
ferred to the transmit shift register, this bit is set to 1. This bit is written to one to abort the trans-
mission of data being held in the transmit data register.
0 = Transmit Data Register is full.
1 = Transmit Data Register is empty.
R/W1C
RDRF
7
0
The Status Register (DBGSTAT) contains status information about the state of the UART.
R/W1C
RXOV
6
0
R/W1C
RXFE
5
0
P R E L I M I N A R Y
RXBRK
R/W1C
4
0
FF_E085
R/W1S
TDRE
Z16FMC Series Motor Control MCUs
3
1
TXCOL
R/W1C
2
0
Product Specification
RXBUSY
On-Chip Debugger
R
1
0
TXBUSY
R
0
0
275
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